Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Abstract: A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.

Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Abstract: A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.

Abstract: A device (45) receives new program files (46) and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine (50) in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory (56) of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory (52) is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Abstract: A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.

Abstract: A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector.

Abstract: A method and system for performing floating-point division of a dividend by a divisor within a floating-point unit having multiply and add functions are disclosed. In performing floating-point division, a quotient having a mantissa is produced. The method uses an approximation based on a linear approximation stored within a first table. The first approximation approximates two divided by the divisor. A second table value is also selected from the table lookup. The second table value approximates the reciprocal of the divisor squared. Both the first and second table values operate as linear correction terms. Also according to the present invention, a method and system are disclosed that perform an early exit check during the division operation to confirm whether the resultant quotient has an acceptable accuracy and if the accuracy is unacceptable, then perform a rounding correction based upon a given rounding boundary.