Abstract: A system and method of identifying objects is provided. In one aspect, the system and method includes a hand-held device with a display, camera and processor. As the camera captures images and displays them on the display, the processor compares the information retrieved in connection with one image with information retrieved in connection with subsequent images. The processor uses the result of such comparison to determine the object that is likely to be of greatest interest to the user. The display simultaneously displays the images the images as they are captured, the location of the object in an image, and information retrieved for the object.

Abstract: A subassembly for a bottom hole assembly of a drill string, the subassembly comprising: a tubular portion having a wall for supporting one or more sensors and an inner surface defining a longitudinal bore; a probe assembly comprising a main body, the probe assembly being removably located in the bore and positioned such that a flow channel for drilling fluid is defined between the inner surface of the tubular portion and the probe assembly. A power link for transferring electrical power between the probe assembly and a sensor supported by the tubular portion.

Abstract: A subassembly for a bottom hole assembly of a drill string, the subassembly comprising: a tubular portion having a wall for supporting one or more sensors and an inner surface defining a longitudinal bore; a probe assembly comprising a main body, the probe assembly being removably located in the bore and positioned such that a flow channel for drilling fluid is defined between the inner surface of the tubular portion and the probe assembly. A communications link for data transfer between the probe assembly and a sensor supported by the tubular portion.

Abstract: A subassembly for a bottom hole assembly of a drill string, the subassembly comprising: a tubular portion having a wall for supporting one or more sensors and an inner surface defining a longitudinal bore; a probe assembly comprising a main body, the probe assembly being removably located in the bore and positioned such that a flow channel for drilling fluid is defined between the inner surface of the tubular portion and the probe assembly. A communications link for data transfer between the probe assembly and a sensor supported by the tubular portion.

Abstract: A subassembly for a bottom hole assembly of a drill string, the subassembly comprising: a tubular portion having a wall for supporting one or more sensors and an inner surface defining a longitudinal bore; a probe assembly comprising a main body, the probe assembly being removably located in the bore and positioned such that a flow channel for drilling fluid is defined between the inner surface of the tubular portion and the probe assembly. A power link for transferring electrical power between the probe assembly and a sensor supported by the tubular portion.

Abstract: A circuit and a method of using the circuit for video frame synchronization are provided. The circuit includes a memory having a capacity less than a full video frame and a “first in first out” (FIFO) interface controlling the memory, further removing the post-read buffer in the memory, and overwriting the post-read buffer in the memory with new data. Some embodiments of the circuit for video frame synchronization provide a wide data bus having a high bandwidth interface to the memory circuit to allow reduced memory clock rate. Some embodiments of the circuit further include a processor that produces a clock signal and measures an input data rate. The processor controls the FIFO interface to generate an output data stream at a preselected frequency, with a preselected phase. More generally, other embodiments of the present invention provide a circuit wherein the processor may be used as a data rate converter and video input timing aberration filter.

Abstract: A circuit and a method for using the circuit to provide synchronization between a first video signal and a second video signal are provided, comprising a circuit to capture a first video signal, a circuit to measure the timing format of the first video signal including an input clock and count input Vsync pulses, a circuit to measure a phase difference between the first video signal and the second video signal, a circuit to generate an output video signal comprising a number of output Vsync pulses and an output clock, and a PLL circuit to control the output clock period as a constant ratio of the input Vsync period, and maintain a constant number of output clock periods per a number of input clock periods. Also provided is a system to perform the method as above using the circuit as above, maintaining a constant ratio between the output clock period and a number of input clock periods.

Abstract: A circuit and a method for using the circuit to provide synchronization between a first video signal and a second video signal are provided, comprising a circuit to capture a first video signal, a circuit to measure the timing format of the first video signal including an input clock and count input Vsync pulses, a circuit to measure a phase difference between the first video signal and the second video signal, a circuit to generate an output video signal comprising a number of output Vsync pulses and an output clock, and a PLL circuit to control the output clock period as a constant ratio of the input Vsync period, and maintain a constant number of output clock periods per a number of input clock periods. Also provided is a system to perform the method as above using the circuit as above, maintaining a constant ratio between the output clock period and a number of input clock periods.

Abstract: A circuit and a method of using the circuit for video frame synchronization are provided. The circuit includes a memory having a capacity less than a full video frame and a “first in first out” (FIFO) interface controlling the memory, further removing the post-read buffer in the memory, and overwriting the post-read buffer in the memory with new data. Some embodiments of the circuit for video frame synchronization provide a wide data bus having a high bandwidth interface to the memory circuit to allow reduced memory clock rate. Some embodiments of the circuit further include a processor that produces a clock signal and measures an input data rate. The processor controls the FIFO interface to generate an output data stream at a preselected frequency, with a preselected phase. More generally, other embodiments of the present invention provide a circuit wherein the processor may be used as a data rate converter and video input timing aberration filter.

Abstract: This invention is directed to compounds of formula I ##STR1## wherein R.sup.1 is CN, CH.sub.2 CN, CH.dbd.CHCN, CHO, or CH.dbd.CHCO.sub.2 H;R.sup.2 is aryl lower alkoxy, heteroaryl lower alkoxy, aryl lower alkylthio or heteroaryl lower alkylthio wherein each of the aryl and heteroaryl moieties is optionally substituted;R.sup.3 is halogen;R.sup.4 is optionally substituted aryl or optionally substituted heteroaryl;R.sup.5 is carboxy or an acid isostere;X is oxygen or sulphur; andn is zero or 1; or an N-oxide thereof, prodrug thereof solvate thereof, or pharmaceutically acceptable salt thereof, which compounds have endothelin antagonist activity. The invention is also directed to methods for preparing the compounds of formula I and their pharmaceutical use.

Abstract: This invention is directed to compounds of formula I ##STR1## wherein R.sup.1 is CN, CH.sub.2 CN, CH.dbd.CHCN, CHO, or CH.dbd.CHCO.sub.2 H;R.sup.2 is aryl lower alkoxy, heteroaryl lower alkoxy, aryl lower alkylthio or heteroaryl lower alkylthio wherein each of the aryl and heteroaryl moieties is optionally substituted;R.sup.3 is halogen;R.sup.4 is optionally substituted aryl or optionally substituted heteroaryl;R.sup.5 is carboxy or an acid isostere;X is oxygen or sulphur; andn is zero or 1; or an N-oxide thereof, prodrug thereof solvate thereof, or pharmaceutically acceptable salt thereof, which compounds have endothelin antagonist activity. The invention is also directed to methods for preparing the compounds of formula I and their pharmaceutical use.