Abstract: A mast for a drilling machine is disclosed. The mast includes a frame assembly defining an inner volume to accommodate a drilling assembly of the drilling machine. The frame assembly includes a first beam, a second beam, a plurality of links, a plurality of reinforcement members, and a plate, that combinedly form a truss. The plate defines an opening to facilitate access to the inner volume of the frame assembly.

Abstract: A mast for a drilling machine is disclosed. The mast includes a frame assembly defining an inner volume to accommodate a drilling assembly of the drilling machine. The frame assembly includes a first beam, a second beam, a plurality of links, a plurality of reinforcement members, and a plate, that combinedly form a truss. The plate defines an opening to facilitate access to the inner volume of the frame assembly.

Abstract: With respect to electronic tag location and tracking, this invention solves moving target and two-fold angle ambiguity without the use of bulky antenna arrays. A multi-element antenna system with fore and aft placement of the elements separated by about ¼ to ½ wave provides an angle of arrival. Antenna selection treats the multiple elements as a single electronically translatable element with an omnidirectional pattern. The elements may be oriented to line up with the fuselage of an aircraft. The antenna elements may be skewed from fore to aft to resolve ambiguity observed with static targets. The apparatus uses successive packets whose content is known at the platform's receiver so that the signal correlation functions are directly comparable. Identical successive packets or different packets of the same length and from the same sequence family may be used. The system may be rapidly calibrated with existing system components.

Abstract: A signal processing arrangement adjusts baud timing in a communication system receiver, wherein an information signal comprised of (sin(x))/x function contributions of successively adjacent bits is received via a memoryless channel. The information signal is sampled in accordance with a baud sampling clock signal, to derive successive samples of bits contained in the information signal. The sampling clock signal has a baud sampling clock frequency that is adjusted by a phase locked loop in accordance with a timing error signal. The signal processing arrangement comprises an intersymbol interference (ISI) correlation-driven baud timing recovery scheme which makes use of the fact that, for a given bit, at all instances in time other than where its peak occurs, the channel will contain energy from adjacent bits, so that there will be a substantial correlation of channel energy among successively adjacent bits of a transmitted sequence.

Abstract: A linearized voltage controlled amplifier (VCA) circuit uses the resistance of a gain control MOSFET to control amplifier gain in accordance with a DC gain control voltage. A gain control voltage is applied to the gain control MOSFET's gate through a gate input resistor that forms a voltage divider with a feedback resistor from the output of the amplifier. Since the VCA's output terminal is a low impedance node, the voltage divider network applies most of the gain control voltage to the gate of the gain control MOSFET. Conversely, a small fraction of the amplifier output signal is coupled to the gain control MOSFET's gate, to reduce distortion. The linearized VCA circuit is augmented by a gate drive correction circuit, through which the gain control voltage is coupled to the VCA's gain control MOSFET. The gate drive correction circuit is comprised of a difference amplifier and a compensating MOSFET that is matched with the gain control MOSFET of the VCA circuit for controlling its gate drive voltage.

Abstract: A reduced hardware complexity, reduced computational intensity finite impulse response filter architecture for filtering multiple (quadrature) channels of an RF modem comprises a cascaded arrangement of L data register stages through which respective digitally encoded data sample values of a signal to be filtered are sequentially clocked. Each data register stage has a data capacity greater than twice the code width of a respective digitized channel sample, so that each register stage can store both I and Q channel data. A multiplier unit is coupled to the data register and multiplies both I and Q contents of respective ones of the register stages by respective impulse response coefficient values. The resulting I and Q products are summed into I and Q channel convolutional sums.

Abstract: An electronically controlled variable gain amplifier is disclosed which provides an output signal proportional to the value of an input signal multiplied by a gain factor, where the gain factor is in turn logarithmically proportional to the value of a gain control signal in the form of a digital word. The amplifier includes a capacitor, a sampler for periodically sampling the value of the input signal and storing the sampled value as a voltage on the capacitor, and circuits for periodically exponentially charging the capacitor after the input signal has been stored thereon for a duration which is directly proportional to the magnitude of the gain control signal. Also included is a circuit for periodically sampling and holding the voltage stored on the capacitor after each periodic charge, where the sampled and held voltage is the amplifier output signal.

Abstract: An electronic telephone interface circuit having a simplified, inductorless electronic gyrator circuit which also functions as an amplifying impedance convertor, and further having passive current and voltage limiting protection devices and an extremely fast active current limiting circuit. The system is particularly suitable for coupling a high impedance electronic system to a telephone communications system, and is adapted to permit the interface circuit and the electronic system to be powered solely from the telephone system.