Abstract: High speed digital data correlator utilizing as a summing circuit single bit full adder cells in a synchronous pipelined array arrangement to sum the number of bit matches with a selected correlation word in a serial data stream. Each adder cell has up to three inputs and provides a partial sum by adding up to three bits of equal powers of two. The simple full adder cell architecture minimizes interconnect lengths between the adjacent synchronous stages of the summing circuit and maintains near constant circuit density across the stages. These features contribute to an optimization of the operational speed of the correlator for any given circuit technology. The correlator of the preferred embodiment detects two complementary, mutually exclusive correlation words, using the same correlation circuit.

Abstract: Digital data is received on a plurality of input channels at unrelated, asynchronous input clock rates. The data is multiplexed and transmitted via one or more synchronous parallel channels, together with encoded information related to the original asynchronous input clock rate on each channel. The data received from the synchronous channels is demultiplexed and redistributed to proper output channels and clocked out therefrom at rates derived from the encoded and reconstituted asynchronous clock rate information from each channel.