Abstract: A RF wireless sensor interface (20) interfaces one or more of a variety of sensors (12, 13) to a RF wireless network (11). A power converter (30) of the interface (20) converts a primary power (PPRM) into a DC power (PDC) that is supplied to the sensor(s) (12, 13). A microcontroller (60) of the interface (20) receives sensor detection information (SDI) from the sensor(s) (12, 13) in response to the sensor(s) (12, 13) receiving the DC power (PDC) from the power converter (30). A RF transmitter/transceiver (50) of the interface (20) executes a sensor detection information RF transmission (SDIRF) and/or a sensor control signal RF transmission (SCSRF) to the RF wireless network (11) in response to the microcontroller (60) receiving the sensor detection information (SDI). The power converter (30), the microcontroller (60) and the RF transmitter/transceiver (50) are located within a modular housing (80).

Abstract: A network (20) employs a wireless network topology (30), a wireless network manager (40). Network (20) further employs a wireless device (70) and wireless device manager (80) pairing and/or a wireless system (90) and a wireless system manager (100) pairing. Managers (40, 80) cooperatively control an operating profile and monitor an operational status of the device (70). Managers (40, 100) cooperatively control an operating profile and monitor an operational status of system (90). Manager (40) can be installed on a computer (150, 170) and wirelessly communicate within network (20) via a wireless control device (160, 180) employing a port connector (161, 181) that can be plugged into a port (151, 171) of the computer (150, 170). Device (70) or system (90) can implement a digital ballast (120) that determines an average power consumption of the digital ballast (120) drawn by a power interface (121) of digital ballast (120).

Abstract: A RF wireless sensor interface (20) interfaces one or more of a variety of sensors (12, 13) to a RF wireless network (11). A power converter (30) of the interface (20) converts a primary power (PPRM) into a DC power (PDC) that is supplied to the sensor(s) (12, 13). A microcontroller (60) of the interface (20) receives sensor detection information (SDI) from the sensor(s) (12, 13) in response to the sensor(s) (12, 13) receiving the DC power (PDC) from the power converter (30). A RF transmitter/transceiver (50) of the interface (20) executes a sensor detection information RF transmission (SDIRF) and/or a sensor control signal RF transmission (SCSRF) to the RF wireless network (11) in response to the microcontroller (60) receiving the sensor detection information (SDI). The power converter (30), the microcontroller (60) and the RF transmitter/transceiver (50) are located within a modular housing (80).

Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Abstract: Methods and structure for enhanced bus arbitration providing a priority-based arbitration technique with improved fairness for lower priority devices. In particular, the invention provides a masking feature within the bus arbiter such that all devices simultaneously requesting temporary exclusive control of the shared bus are remembered in the mask when a bus grant is made to a first requesting master device. When the first master device relinquishes control of the bus, remembered master devices are first granted temporary exclusive control of the bus (preferably in priority order) prior to any non-remembered master devices presently requesting the bus. When all remembered master devices have been granted an opportunity for temporary exclusive control of the bus, the mask identifying remembered master devices is cleared and standard priority-based arbitration techniques resume.

Abstract: A set of registers are provided for a protocol engine driving I/O transactions requested by a host. A fixed set of defined data elements are determined for the protocol under which the I/O transaction is to be performed. Each register maps to a data structure base address or to a different data element offset or byte count. During initialization, the registers are programmed by an operating system device driver with offsets from a base address and byte counts for each data element within the defined set as those data elements are found within an operating system specific data structure for the I/O transaction, although data elements having a fixed size for each operating system may not require the byte count to be specified. For each I/O transaction requested, the base address in the host memory of the operating system specific data structure is programmed by the device driver into a register.