Patents by Inventor Andrew C. Chang

Andrew C. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176408
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 4, 2020
    Applicant: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Patent number: 10661795
    Abstract: A device can receive data related to a roadway. The data can include video data of the roadway. The device can determine a pixel area of objects shown in the video data. The device can determine that a vehicle and an individual are associated with the roadway at a same time. The device can determine a protective zone around the individual based on a first pixel area of the individual. The protective zone can be associated with detecting a potential collision between the vehicle and the individual. The device can determine a first location and movement of the vehicle relative to a second location and movement of the individual. The device can predict that a second pixel area of the vehicle is to intersect the protective zone of the individual. The device can detect the potential collision. The device can perform one or more actions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 26, 2020
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Ranxing Li, Paul Brand, Philip C. Jacobs, Fang-Pin Chang, Abby Charfauros, Andrew W. Herson, Sheng S. Du, Amanda UyenTrang Mai, George F. Clernon, Bing Yao, Matthew B. Whited
  • Patent number: 10580747
    Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 3, 2020
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Patent number: 10573615
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: February 25, 2020
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Patent number: 10573616
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: February 25, 2020
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Publication number: 20200000146
    Abstract: A vaporizer device may include various modular components. The vaporizer device may include a first subassembly. The first subassembly may include a cartridge connector that secures a vaporizer cartridge to the vaporizer device and includes at least two receptacle contacts that electrically communicate with the vaporizer cartridge. The vaporizer device may include a second subassembly. The second subassembly may include a skeleton defining a rigid tray that retains at least a power source. The vaporizer device may also include a third subassembly. The third subassembly may include a plurality of charging contacts that supply power to the power source, and an end cap that encloses an end of the vaporizer device.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 2, 2020
    Inventors: Samuel C. Anderson, Wei-Ling Chang, Brandon Cheung, Steven Christensen, Joseph Chun, Joseph R. Fisher, Jr., Nicholas J. Hatton, Kevin Lomeli, James Monsees, Andrew L. Murphy, Claire O' Malley, John R. Pelochino, Hugh Pham, Vipul V. Rahane, Matthew J. Taschner, Val Valentine, Kenneth Wong
  • Publication number: 20190369711
    Abstract: Systems, methods, and computer-readable media for managing near field communications during a low power express mode of an electronic device are provided that may make credentials of a near field communication (“NFC”) component appropriately secure and appropriately accessible while also limiting the power consumption of the NFC component and of other components of the electronic device.
    Type: Application
    Filed: September 11, 2018
    Publication date: December 5, 2019
    Inventors: Yong Wang, Gordon Y. Scott, Andrew C. Chang, Scott A. Williams
  • Patent number: 10354974
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 16, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Andrew C. Chang, Tao Cheng
  • Patent number: 10186488
    Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 22, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Publication number: 20170338183
    Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Patent number: 9761534
    Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 12, 2017
    Assignee: MEDIATEK INC.
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Publication number: 20170084541
    Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.
    Type: Application
    Filed: May 24, 2016
    Publication date: March 23, 2017
    Inventors: Wen-Sung Hsu, Shih-Chin Lin, Tao Cheng, Andrew C. Chang
  • Publication number: 20160307861
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Applicant: Media Tek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Publication number: 20160172334
    Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.
    Type: Application
    Filed: June 11, 2015
    Publication date: June 16, 2016
    Inventors: Wen-Sung HSU, Shih-Chin LIN, Andrew C. CHANG, Tao CHENG
  • Patent number: 9177899
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 3, 2015
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Patent number: 9040359
    Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
  • Patent number: 8957518
    Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 17, 2015
    Assignee: Mediatek Inc.
    Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
  • Publication number: 20140377913
    Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Inventors: Thomas Matthew GREGORICH, Andrew C. CHANG, Tzu-Hung LIN
  • Patent number: 8859340
    Abstract: A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 14, 2014
    Assignee: MediaTek Inc.
    Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
  • Publication number: 20140191396
    Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.
    Type: Application
    Filed: March 12, 2014
    Publication date: July 10, 2014
    Applicant: MEDIA TEK INC.
    Inventors: Tzu-Hung LIN, Wen-Sung HSU, Ta-Jen YU, Andrew C. CHANG