Abstract: A method performs automated at-speed testing of devices. The method includes the steps of generating multiplexer control signals, forming various signal paths between a set of multiplexers and the devices based on the multiplexer control signals, and routing test signals having multiple gigabit per second (MGBPS) baud rates through the signal paths.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The system includes a test head including a device interface board (DIB), the DIB having a device under test holding device for coupling the devices to the DIB. The system also includes a rider board including a multiplexing system coupled to a control system and to the DIB, the rider board being configured to route a serial data test signal having multi-gigabit per second baud rate through one or more of the devices.

Abstract: A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external testing system to the portion of the test head, a restricted section positioned between said connection sections, a device interface board (DIB) having a device under test (DUT) holding section that secures the devices, said DIB positioned below said restriction section and a multi-layered rider board coupled to the devices via a coupling section, said rider board forming signal paths to route testing signals between at least the devices and the external testing system.

Abstract: A testing system performs simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates coupled to a DIB and device connectors on the DIB. The testing system includes a rider board including rider board connectors coupled to corresponding ones of the device connectors, an individual set of multiplexers coupled to each one of said rider board connectors, a controller coupled to each of said set of multiplexers, and an internal testing system including a tester and testing system multiplexers, said tester being coupled to each of said set of multiplexers via said testing system multiplexers.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: A system performs automated at-speed testing of a plurality of devices that generate serial data signals having multiple gigabit per second baud rates. The system includes a test head including a device interface board (DIB), the DIB having a device under test holding device for coupling the devices to the DIB. The system also includes a rider board including a multiplexing system coupled to a control system and to the DIB, the rider board being configured to route a serial data test signal having multi-gigabit per second baud rate through one or more of the devices.

Abstract: A portion of a test head utilized to perform simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates. The portion of the test head includes connection sections that couple an external testing system to the portion of the test head, a restricted section positioned between said connection sections, a device interface board (DIB) having a device under test (DUT) holding section that secures the devices, said DIB positioned below said restriction section and a multi-layered rider board coupled to the devices via a coupling section, said rider board forming signal paths to route testing signals between at least the devices and the external testing system.

Abstract: A testing system performs simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates coupled to a DIB and device connectors on the DIB. The testing system includes a rider board including rider board connectors coupled to corresponding ones of the device connectors, an individual set of multiplexers coupled to each one of said rider board connectors, a controller coupled to each of said set of multiplexers, and an internal testing system including a tester and testing system multiplexers, said tester being coupled to each of said set of multiplexers via said testing system multiplexers.

Abstract: A method performs automated at-speed testing of devices. The method includes the steps of generating multiplexer control signals, forming various signal paths between a set of multiplexers and the devices based on the multiplexer control signals, and routing test signals having multiple gigabit per second (MGBPS) baud rates through the signal paths.