Abstract: Techniques for use with a processor configured to function as at least a Mapper in a MapReduce system include generating a set of [key, value] pairs by executing a Map function on input data. The set of [key, value] pairs may be stored in a storage system implemented on at least one data storage medium, the storage system being organized into a plurality of divisions with different divisions of the storage system storing [key, value] pairs corresponding to different keys. A first [key, value] pair corresponding to a first key handled by a first Reducer in the MapReduce system and a second [key, value] pair corresponding to a second key handled by a second Reducer in the MapReduce system may both be stored in a first division of the plurality of divisions.

Abstract: A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor.

Abstract: An automated method of optimizing execution of a program in a parallel processing environment is described. The program is adapted to execute in data memory and instruction memory. An optimizer receives the program to be optimized. The optimizer instructs the program to be compiled and executed. The optimizer observes execution of the program and identifies a subset of instructions that execute most often. The optimizer also identifies groups of instructions associated with the subset of instructions that execute most often. The identified groups of instructions include the identified subset of instructions that execute most often. The optimizer recompiles the program and stores the identified groups of instructions in instruction memory. The remaining instructions portions of the program are stored in the data memory. The instruction memory has a higher access rate and smaller capacity than the data memory. Once recompiled, subsequent execution of the program occurs using the recompiled program.

Abstract: A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.

Abstract: An automated method of performing exponentiation is disclosed. A plurality of tables holding factors for obtaining results of Exponentiations are provided. The plurality of tables are loaded into computer memory. Each factor is the result of a second exponentiation of a constant and an exponent. The exponent is related to a memory address corresponding to the factor. A plurality of memory addresses are identified for performing the first exponentiation by breaking up the first exponentiation into equations, the results of which are factors of the first Exponentiation. The exponents of the equations are related to the memory addresses corresponding to the factors held in the tables. A plurality of lookups into the computer memory are performed to retrieve the factors held in the tables corresponding to the respective memory addresses. The retrieved factors are multiplied together to obtain the result of the first exponentiation.

Abstract: A system and associated methods are disclosed for allocating memory in a system providing translation of virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a request for memory allocation, identifying an available virtually-contiguous physically-non-contiguous memory region (VCPNCMR) of at least the requested size, where the VCPNCMR is arranged such that physical memory addresses for the VCPNCMR may be derived from a corresponding virtual memory addresses by shifting a contiguous set of bits of the virtual memory address in accordance with information in a matching row of a virtual memory address matching table, and combining the shifted bits with high-order physical memory address bits also associated with the determined matching row and with low-order bits of the virtual memory address, and providing to the requesting process a starting address of the identified VCPNCMR.

Abstract: This invention provides a computer and/or processor architecture optimized for power-efficient computation of a class of sensory recognition (e.g. vision) algorithms on a single computer chip derived from research into how humans process sensory information, such as vision. The processor for efficiently recognizing sensory information with recognizable features defines a feature recognition engine that resolves features from the sensory information and provides a feature information input. A plurality of processing nodes, arranged in a hierarchy of layers, receives the input and, in parallel, recognizes multiple components of the features. Recognized features are transferred between the layers so as to build likely recognition candidates and remove unlikely recognition candidates. A memory in each of the nodes refreshes and retains predetermined features related to likely recognition candidates as the features are transferred between the layers.

Abstract: A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor.

Abstract: Techniques for use with at least one processor configured to execute one or more MapReduce applications that cause the at least one processor to function as at least a Mapper in a MapReduce system include accessing data stored in a file system implemented on at least one nonvolatile storage medium. In response to input data being written to the file system by an application other than the one or more MapReduce applications, a set of one or more Map functions applicable to the input data may be accessed. At least one Map function of the one or more Map functions may be executed on the input data via the at least one processor functioning as at least the Mapper in the MapReduce system, and at least one set of [key, value] pairs resulting from execution of the at least one Map function on the received input data may be output.

Abstract: In some embodiments, a processor configured to function as at least a first Reducer in a MapReduce system may receive a set of mapped [key, value] pairs output from a Mapper in the MapReduce system, identify within the set of mapped [key, value] pairs one or more [key, value] pairs for whose keys the first Reducer is not responsible, and transfer those [key, value] pairs to one or more other Reducers in the MapReduce system. In some embodiments, a system including at least one processor may receive a data packet including a set of mapped [key, value] pairs corresponding to a plurality of keys handled by a plurality of Reducers in a MapReduce system. For each mapped [key, value] pair, the system may identify the corresponding key and one of the Reducers responsible for that key, and provide the mapped [key, value] pair to the Reducer for processing.

Abstract: Techniques for use with a processor configured to function as at least a Mapper in a MapReduce system include generating a set of [key, value] pairs by executing a Map function on input data. The set of [key, value] pairs may be stored in a storage system implemented on at least one data storage medium, the storage system being organized into a plurality of divisions with different divisions of the storage system storing [key, value] pairs corresponding to different keys. A first [key, value] pair corresponding to a first key handled by a first Reducer in the MapReduce system and a second [key, value] pair corresponding to a second key handled by a second Reducer in the MapReduce system may both be stored in a first division of the plurality of divisions.

Abstract: A system and methods are provided for interactive construction of data queries.

Abstract: A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor.

Abstract: A system and associated methods are disclosed for allocating memory in a system providing translation of virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a request for memory allocation, identifying an available virtually-contiguous physically-non-contiguous memory region (VCPNCMR) of at least the requested size, where the VCPNCMR is arranged such that physical memory addresses for the VCPNCMR may be derived from a corresponding virtual memory addresses by shifting a contiguous set of bits of the virtual memory address in accordance with information in a matching row of a virtual memory address matching table, and combining the shifted bits with high-order physical memory address bits also associated with the determined matching row and with low-order bits of the virtual memory address, and providing to the requesting process a starting address of the identified VCPNCMR.

Abstract: A system and associated methods are disclosed for routing communications amongst computing units in a distributed computing system. In a preferred embodiment, processors engaged in a distributed computing task transmit results of portions of the computing task via a tree of network switches. Data transmissions comprising computational results from the processors are aggregated and sent to other processors via a broadcast medium. Processors receive information regarding when they should receive data from the broadcast medium and activate receivers accordingly. Results from other processors are then used in computation of further results.

Abstract: A system and associated methods are disclosed for translating virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a virtual memory address, comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table, determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address, shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information from the matching row, and combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address.

Abstract: A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.

Abstract: A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.

Abstract: A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an integer greater than 1. The processor core implements n virtual processors, a pipeline having p ordered stages, including a memory operation stage, and a virtual processor selector function.

Abstract: This invention provides a computer processor architecture optimized for power-efficient computation of certain sensory recognition (e.g. vision) algorithms on a single computer chip. Illustratively, the architecture is optimized to carry out low-level routines and a special class of high-level sensory recognition routines derived from research into human brain perception processes. In an illustrative embodiment, the processor includes a plurality of processing nodes, arranged in a hierarchy of layers, and the processor resolves features from sensory information input and provides the feature information as input to a lowest hierarchy layer thereof. The hierarchy simultaneously, recognizes multiple components of the features, which are transferred between the layers so as to build likely recognition candidates. Each node can further include memory constructed and arranged to refresh and retain features determined to be likely recognition candidates by a thresholding process.