Abstract: This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Abstract: A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.

Abstract: This invention discloses a laser programmable read only semiconductor-based memory array comprised of memory cells, a group of word lines, a group of bit lines. Each of the memory cells is connected to one of the group of bit lines, and one of the group of word lines and each memory cell is comprised of a memory element and a laser programmable link. In one embodiment, each memory cell is comprised of a transistor and a laser programmable link composed of the same material as either the word or the bit lines. Programming is accomplished by laser coding of the links.

Abstract: This invention discloses an oscillator circuit wholly contained in a single integrated circuit and implemented in compound semiconductor technology, wherein the oscillation frequency thereof is substantially stable over variations in supply voltage, process variations in fabrication, and temperature.

Abstract: This invention discloses an integrated circuit implemented in compound semiconductor technology including an input signal lead and an output signal lead, and buffer circuitry interconnecting those leads, the circuit being compatible with standard logic signals thereinto and therefrom.

Abstract: This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Abstract: This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.

Abstract: This invention discloses a TTL compatible output buffer circuit which provides that in the state where the output signal thereof is high, no substantial current is provided inward of the buffer circuit from the output signal lead over a wide range of voltages applied to the output signal lead, including applied voltages substantially greater than that supplied by the voltage supply terminals of the circuit, with the circuit being further implemented in compound semiconductor technology.

Abstract: This invention discloses a TTL compatible input buffer which includes means for preventing appreciable current flow into the buffer circuit upon input voltage being supplied to the input signal lead which is substantially above the voltages supplied to the voltage supply terminals of the circuit.

Abstract: A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit to determine the implementation of redundant elements in a semiconductor memory. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array.

Abstract: A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array.

Abstract: A battery backup circuit for an MOS memory which has a multiplexed pin (WE) that functions to provide backup power to a memory cell array (50) upon loss of primary power V.sub.cc. A voltage comparator (10) detects when the primary power V.sub.cc becomes less than the backup voltage on the WE terminal. Upon detection of loss of primary power the memory cell array (50) is powered by a connection to the WE terminal. A primary power status signal (POK) indicates the status of the primary power and is driven to a state indicating insufficient circuit voltage for normal operation when V.sub.cc drops below an acceptable limit or when there is inadequate substrate bias. The circuit of the present invention further generates an inhibit signal to prevent the operation of peripheral circuits (70) to write data into the memory cell array (50) upon detection of a failure of primary power. The inhibit signal is generated when primary power is lost or when the substrate bias is inadequate.