Abstract: A fluid heating element includes first and second conduits. The first conduit has a first inlet and a first outlet. The first inlet is configured to receive a first portion of the fluid, and the first outlet is configured to discharge the first portion of the fluid. The second conduit has a second inlet and a second outlet. The second inlet is configured to receive a second portion of the fluid, and the second outlet is configured to discharge the second portion of the fluid. The fluid heating element further includes an electrothermal coating associated with the first and second conduits and an electrical lead configured to apply an electric current across the electrothermal coating. The electrothermal coating converts the electric current to heat that is transferred to through the first and second conduits to the fluid.

Abstract: A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the first conductive pattern of the flex circuit such that the integrated circuit chip packages are positioned upon respective ones of opposed top and bottom surfaces of the flex substrate. Alternatively, one of the integrated circuit chip packages may be positioned upon the top surface of the flex substrate and electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached in a non-conductive manner to the bottom surface of the flex substrate such that the conductive contacts of such integrated circuit chip package and the leads collectively define a composite footprint for the chip stack.

Abstract: A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the first conductive pattern of the flex circuit such that the integrated circuit chip packages are positioned upon respective ones of opposed top and bottom surfaces of the flex substrate. Alternatively, one of the integrated circuit chip packages may be positioned upon the top surface of the flex substrate and electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached in a non-conductive manner to the bottom surface of the flex substrate such that the conductive contacts of such integrated circuit chip package and the leads collectively define a composite footprint for the chip stack.

Abstract: A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.

Abstract: A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.

Abstract: A connector for use in a chip stack including at least first and second stacked packaged chips which each comprise a package body having a plurality of leads extending therefrom. The connector comprises a substrate which is preferably fabricated from an insulating material. Attached to the substrate are a plurality of flex tabs which extend in spaced relation to each other, and are each preferably fabricated from a conductive material such as aluminum. The flex tabs are each shaped to define an arcuately contoured first portion which is electrically connectable to a respective one of the leads of the first packaged chip, and an integral, generally flat second portion which extends along a portion of the substrate and is electrically connectable to a corresponding one of the leads of the second packaged chip.

Abstract: A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the first conductive pattern of the flex circuit such that the integrated circuit chip packages are positioned upon respective ones of opposed top and bottom surfaces of the flex substrate. Alternatively, one of the integrated circuit chip packages may be positioned upon the top surface of the flex substrate and electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached in a non-conductive manner to the bottom surface of the flex substrate such that the conductive contacts of such integrated circuit chip package and the leads collectively define a composite footprint for the chip stack.

Abstract: A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.

Abstract: A stackable integrated circuit chip package comprising an interconnect sub-assembly which includes an interconnect substrate having first, second and third conductive pad arrays disposed thereon. The interconnect sub-assembly also includes a first rail member which is attached to the interconnect substrate and has a fourth conductive pad array disposed thereon, and a second rail member which is also attached to the interconnect substrate and has a fifth conductive pad array disposed thereon. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays of the interconnect substrate. In addition to the interconnect sub-assembly, the chip package of the present invention includes an integrated circuit chip which is electrically connected to the first conductive pad array of the interconnect substrate of the interconnect sub-assembly.

Abstract: A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame.

Abstract: A chip module comprising a chip array which includes an interconnect substrate having opposed, generally planar surfaces and a first interconnect pad array disposed on at least one of the surfaces thereof. Attached to the interconnect substrate is at least one integrated circuit chip of the chip array which is electrically connected to the first interconnect pad array. The chip module further comprises a package which itself comprises a main body defining a cavity sized and configured to receive the chip array and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package also includes a lid which is attachable to the main body. The chip array is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of the lid to the main body encloses and seals the chip array within the package.

Abstract: A chip module comprising a chip array which includes an interconnect substrate having opposed, generally planar surfaces and a first interconnect pad array disposed on at least one of the surfaces thereof. Attached to the interconnect substrate is at least one integrated circuit chip of the chip array which is electrically connected to the first interconnect pad array. The chip module further comprises a package which itself comprises a main body defining a cavity sized and configured to receive the chip array and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package also includes a lid which is attachable to the main body. The chip array is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of the lid to the main body encloses and seals the chip array within the package.