Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Abstract: System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Abstract: A device for configuring a serial ROM. In accordance thereto, a read instruction is serially transmitted to the input of the serial ROM. Thereafter, an x-bit address of all zeros is serially transmitted to the input of the serial ROM. Each bit of the instruction and x-bit address is transmitted to the input of this serial ROM on a rising edge of a clock also inputted to the serial ROM. The output of the serial ROM is connected to a precharged sense node. Prior to the serial ROM outputting data in response to the x-bit address, the serial ROM will discharge the sense node to ground if the serial ROM is one of the first type of serial ROMs. However, if the serial ROM is a second type, the sensing node will not be discharged to ground prior to output of the data. Immediately after transmission of the x-bit address, a configuration register is set to indicate the type of serial ROM.

Abstract: A GPIB bus extender which intelligently supports the IEEE 488.2 find listeners protocol. The GPIB bus extender of the present invention monitors the bus and determines when a talker is present on the bus. When the GPIB extender detects a talker present on the bus, the extender configures itself as a listener to receive any messages for devices on the remote bus. When the GPIB extender does not detect a talker present on the bus, the extender does not configure itself as a listener, but rather is prepared to participate in a find listener protocol.

Abstract: A modified IEEE 488.1 bus interface increases, by as much as a factor of eight, the rate at which inter-instrument data transfers can be performed. The bus interface state machines presented in the ANSI/IEEE Std 488.1-1987 have been modified so that if all the devices involved in a particular data transfer are equipped to handle high speed data transfers, then a modified data transmission methodology is used so as to enable multiline messages to be transmitted at a higher speed than would otherwise be possible. If any of the devices involved in a particular data transfer does not have an interface equipped to handle high speed data transfers, this condition is automatically detected by the interfaces with high speed capability, and then the standard data transmission methodology is used. The high speed data transmission mode is totally transparent to the controller software in that it does not require any changes to the controller software nor to the device drivers and device application programs.