Abstract: A method of creating multi-gate transistors with integrated circuit polygon compactors is disclosed. Specifically, in order to provide a more efficient layout when the size of a transistor is increased during design migration, a small multi-gate transistor is formed by inserting at least one parallel transistor over the diffusion layer of the target transistor, between a gate and contact. The compactor then enforces the new design rules, and adjusts the relative sizes of the parallel transistors as required. The resulting multi-gate transistor structure is much more compact than a single large transistor, providing a more efficient design layout.

Abstract: A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g.

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

Abstract: Defects in dielectric layers exhibiting low dielectric strength on silicon substrates (11) are deliberately damaged during manufacture to allow their repair by the formation of dielectric plugs (13B). The defects are damaged by the application of an electric field, and are repaired by the selective oxidation or nitridation of the silicon substrate underlying the damaged areas of dielectrics.

Abstract: A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region.

Abstract: An electrically erasable programmable read-only memory (E.sup.2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E.sup.2 PROM array consists of a single floating gate field effect transistor. The E.sup.2 PROM of the present invention provides for row erasure and single bit writing.