Abstract: An acoustic imaging system coupled to a sensing plate to define an imaging surface. The acoustic imaging system includes an array of piezoelectric acoustic transducers coupled to the sensing plate opposite the imaging surface and formed using a thin-film manufacturing process over an application-specific integrated circuit that, in turn, is configured to leverage the array of piezoelectric actuators to generate an image of an object at least partially wetting to the imaging surface.

Abstract: Compositions and methods related to powdered hemostats that crosslink during and/or after application to a bleeding site are generally described.

Abstract: Compositions and methods related to powdered hemostats that crosslink during and/or after application to a bleeding site are generally described.

Abstract: Compositions and methods related to flowable hemostats that crosslink during and/or after application to a bleeding site are generally described.

Abstract: Compositions and methods related to powdered hemostats that crosslink during and/or after application to a bleeding site are generally described.

Abstract: Disclosed herein are novel synthetic bacteriophages and bacteriophage compositions, methods of production thereof, and therapeutic uses thereof.

Abstract: Disclosed herein are novel synthetic bacteriophages and bacteriophage compositions, methods of production thereof, and therapeutic uses thereof.

Abstract: Disclosed herein are novel synthetic bacteriophages and bacteriophage compositions, methods of production thereof, and therapeutic uses thereof.

Abstract: Disclosed herein are novel synthetic bacteriophages and bacteriophage compositions, methods of production thereof, and therapeutic uses thereof.

Abstract: A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the plurality of processing units, and a link coupled between the first and second network interface units. The first and second network interface units each includes an independently controllable network port for connection to a network, and a virtual interface. The network port includes a shared MAC unit, a link interface, and control logic, which may selectably route packets between processing units of the first portion of the plurality of processing units and the network via the link and the network port of the second network interface unit. The virtual interface may include a plurality of independent programmable virtual MAC units.

Abstract: A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of the network port between the one or more processing units. The network port may include a shared media access control (MAC) unit. The virtual interface may include a plurality of processing unit resources each associated with a respective one of the one or more processing units. Each of the processing unit resources may include an I/O interface unit coupled to a respective one of the one or more processing units via an I/O interconnect, and an independent programmable virtual MAC unit that is programmably configured by the respective one of the one or more processing units.

Abstract: A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.

Abstract: A system includes one or more processing units coupled to a network interface unit. The network interface unit may include a network port for connection to a network and a virtual interface that may be configured to distribute an available communication bandwidth of the network port between the one or more processing units. The network port may include a shared media access control (MAC) unit. The virtual interface may include a plurality of processing unit resources each associated with a respective one of the one or more processing units. Each of the processing unit resources may include an I/O interface unit coupled to a respective one of the one or more processing units via an I/O interconnect, and an independent programmable virtual MAC unit that is programmably configured by the respective one of the one or more processing units.

Abstract: A system for sharing a network port of a network interface includes a plurality of processing units, a first network interface unit coupled to a first portion of the plurality of processing units, a second network interface unit coupled to a different portion of the plurality of processing units, and a link coupled between the first and second network interface units. The first and second network interface units each includes an independently controllable network port for connection to a network, and a virtual interface. The network port includes a shared MAC unit, a link interface, and control logic, which may selectably route packets between processing units of the first portion of the plurality of processing units and the network via the link and the network port of the second network interface unit. The virtual interface may include a plurality of independent programmable virtual MAC units.

Abstract: A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

Abstract: The invention comprises a Schottky barrier type infrared photodetector which is monolithically integrated on a silicon waveguide. A Schottky barrier contact is positioned directly on a silicon waveguide to absorb grazing incidence optical signals passing through the waveguide. The Schottky contact is operated in the avalanche or reverse bias mode to generate a useable electrical signal.

Abstract: A mode dependent, optical time delay system for electrical signals having a highly multi-mode optical fiber having a step index profile in optical alignment with an optical source which is capable of converting an incoming electrical signal into an optical signal. By incorporating within the system a number of different components to alter or control the mode angles of the incoming optical signal, the resultant optical output signal is time delayed as it propagates through the optical fiber. This optical output signal is thereafter converted into an electrical output signal which is also time delayed in direct relation to the mode angle of the optical signal propagating through the optical fiber.

Abstract: A solid state sensing retina for infrared vidicon television camera tubes using a low voltage electron beam, consisting of a monolithic silicon wafer having an n-type substrate and two dimensional array of p-type islands, each island has a Schottky electrode photoemitter and substrate contact buss, an ohmic contact pad allows charging of the p-type region beneath the Schottky electrode.