Patents by Inventor Andrew Calvano

Andrew Calvano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parallel data flow analysis processing to stage automated vulnerability research
    Patent number: 10891216
    Abstract: A method for data flow analysis, comprising: obtaining, by a processing circuitry, an execution trace of a software program; dividing, by the processing circuitry, the execution trace into a plurality of sections; generating a plurality of definition-and-usage chains, at least some of the definition-and-usage chains being generated by different processors, at least some of the definition-and-usage chains being generated based on different sections of the execution trace, at least two of the definition-and-usage chains being generated in parallel with one another; combining, by the processing circuitry, the plurality of definition-and-usage chains to produce a data flow graph, the definition-and-usage chains being combined based on information provided by at least one of the processors that are used to generate the definition-and-usage chains, the information indicating one or more unresolved memory locations that are accessed by respective operations corresponding to one or more incomplete usage nodes in the
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 12, 2021
    Assignee: Raytheon Company
    Inventor: Andrew Calvano
  • PARALLEL DATA FLOW ANALYSIS PROCESSING TO STAGE AUTOMATED VULNERABILITY RESEARCH
    Publication number: 20200201742
    Abstract: A method for data flow analysis, comprising: obtaining, by a processing circuitry, an execution trace of a software program; dividing, by the processing circuitry, the execution trace into a plurality of sections; generating a plurality of definition-and-usage chains, at least some of the definition-and-usage chains being generated by different processors, at least some of the definition-and-usage chains being generated based on different sections of the execution trace, at least two of the definition-and-usage chains being generated in parallel with one another; combining, by the processing circuitry, the plurality of definition-and-usage chains to produce a data flow graph, the definition-and-usage chains being combined based on information provided by at least one of the processors that are used to generate the definition-and-usage chains, the information indicating one or more unresolved memory locations that are accessed by respective operations corresponding to one or more incomplete usage nodes in the
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Raytheon Company
    Inventor: Andrew Calvano