Patents by Inventor Andrew Camien

Andrew Camien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100291735
    Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Inventors: Volkan Ozguz, Angel Pepe, James Yamaguchi, W. Eric Boyd, Douglas Albert, Andrew Camien
  • Patent number: 7786562
    Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: August 31, 2010
    Inventors: Volkan Ozguz, Angel Pepe, James Yamaguchi, W. Eric Boyd, Douglas Albert, Andrew Camien
  • Publication number: 20050277288
    Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 15, 2005
    Inventors: Volkan Ozguz, Angel Pepe, James Yamaguchi, W. Boyd, Douglas Albert, Andrew Camien
  • Publication number: 20040113222
    Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metalization reroute from the user-selected bond pads and vias is applied. The inactive surface of the wafer may be back thinned if desired. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
    Type: Application
    Filed: September 16, 2003
    Publication date: June 17, 2004
    Inventors: Volkan H. Ozguz, Angel A. Pepe, James Yamaguchi, Andrew Camien, Douglas M. Albert