Patents by Inventor Andrew Cao
Andrew Cao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10403510Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.Type: GrantFiled: June 19, 2017Date of Patent: September 3, 2019Assignee: Invensas CorporationInventors: Andrew Cao, Michael Newman
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Patent number: 10381326Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.Type: GrantFiled: May 28, 2014Date of Patent: August 13, 2019Assignee: Invensas CorporationInventors: Charles G. Woychik, Arkalgud R. Sitaram, Andrew Cao, Bong-Sub Lee
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Publication number: 20170294321Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Applicant: Invensas CorporationInventors: Andrew Cao, Michael Newman
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Patent number: 9691693Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.Type: GrantFiled: December 4, 2013Date of Patent: June 27, 2017Assignee: Invensas CorporationInventors: Andrew Cao, Michael Newman
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Publication number: 20150348940Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Inventors: Charles G. WOYCHIK, Arkalgud R. Sitaram, Andrew Cao, Bong-Sub Lee
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Publication number: 20150155230Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.Type: ApplicationFiled: December 4, 2013Publication date: June 4, 2015Applicant: INVENSAS CORPORATIONInventors: Andrew Cao, Michael Newman
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Patent number: 7602641Abstract: A method of making a non-volatile memory (NVM) cell structure includes the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell.Type: GrantFiled: September 25, 2008Date of Patent: October 13, 2009Assignee: National Semiconductor CorporationInventors: Pavel Poplevine, Annie-Li-Keow Lum, Andrew Cao, Ernes Ho
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Publication number: 20090129162Abstract: A method of making a non-volatile memory (NVM) cell structure comprises the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell.Type: ApplicationFiled: September 25, 2008Publication date: May 21, 2009Inventors: Pavel Poplevine, Annie-Li-Keow Lum, Andrew Cao, Ernes Ho
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Patent number: 7482634Abstract: The present invention is directed towards a source of ultraviolet energy, wherein the source is a UV-emitting LED's. In an embodiment of the invention, the UV-LED's are characterized by a base layer material including a substrate, a p-doped semiconductor material, a multiple quantum well, a n-doped semiconductor material, upon which base material a p-type metal resides and wherein the base structure has a mesa configuration, which mesa configuration may be rounded on a boundary surface, or which may be non-rounded, such as a mesa having an upper boundary surface that is flat. In other words, the p-type metal resides upon a mesa formed out of the base structure materials. In a more specific embodiment, the UV-LED structure includes n-type metallization layer, passivation layers, and bond pads positioned at appropriate locations of the device. In a more specific embodiment, the p-type metal layer is encapsulated in the encapsulating layer.Type: GrantFiled: September 24, 2004Date of Patent: January 27, 2009Assignee: Lockheed Martin CorporationInventors: Robert John Wojnarowski, Stanton Earl Weaver, Jr., Abasifreke Udo Ebong, Xian An (Andrew) Cao, Steven Francis LeBoeuf, Larry Burton Rowland, Stephen D. Arthur
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Patent number: 7453726Abstract: A single 4-transistor non-volatile memory (NVM) cell includes a shared static random access memory cell. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the shared SRAM cell structure, allows an entire cell array to be programmed at two cycles. A single NVM cell approach with shared SRAM allows a 50% area reduction with an insignificant increase in program time.Type: GrantFiled: January 23, 2007Date of Patent: November 18, 2008Assignee: National Semiconductor CorporationInventors: Pavel Poplevine, Annie-Li-Keow Lum, Andrew Cao, Ernes Ho
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Publication number: 20070018659Abstract: An apparatus for measuring fluid resistivity includes a flow line adapted to be in fluid communication with formation fluids, wherein the flow line includes a first section comprising a first conductive area, a second section comprising a second conductive area, and an insulating section disposed between the first section and the second section to prevent direct electrical communication between the first section and the second section; a first toroid and a second toroid surrounding the flow line around the first section and the second section, respectively, wherein the first toroid is configured to induce an electrical current in a fluid in the flow line and the second toroid is configured to measure the electrical current induced in the fluid in the flow line; and an electronic package to control functions of the first toroid and the second toroid.Type: ApplicationFiled: July 19, 2005Publication date: January 25, 2007Inventors: Dean Homan, Andrew Cao, Brian Clark