Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

Abstract: A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.

Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

Abstract: The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.

Abstract: A data and clock recovery circuit includes a first selecting circuit, a high speed phase detector, a low speed phase detector, a charge pump, a voltage control oscillator and a frequency divider. The high speed phase detector generates a first phase difference signal according to the first reference clock signal and a divided clock signal or according to the data signal and the divided clock signal. The low speed phase detector generates a second phase difference signal according to a second reference clock signal and the divided clock signal. The charge pump generates a control voltage according to the first phase difference signal or the second phase difference signal. The voltage control oscillator receives the control voltage, and generates a recovered clock signal. The frequency divider receives the recovered clock signal, and generates the divided clock signal.

Abstract: A method of managing a buffer (or buffer memory) includes utilizing one or more shared pool buffers, one or more port/priority buffers and a global multicast pool. When packets are received, a shared pool buffer is utilized; however, if a packet does not fit in the shared pool buffer, then the appropriate port/priority buffer is used. If the packet is a multicast packet, then the global multicast pool is utilized for copies of the packet.

Abstract: A method of managing a buffer (or buffer memory) includes utilizing one or more shared pool buffers, one or more port/priority buffers and a global multicast pool. When packets are received, a shared pool buffer is utilized; however, if a packet does not fit in the shared pool buffer, then the appropriate port/priority buffer is used. If the packet is a multicast packet, then the global multicast pool is utilized for copies of the packet.