Patents by Inventor Andrew Christopher Graeme Wood

Andrew Christopher Graeme Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127853
    Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Infineon Technologies AG
    Inventors: Cristian Mihai Boianceanu, Liu Chen, Sebastian Sosin, Andrew Christopher Graeme Wood
  • Publication number: 20210265497
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
  • Patent number: 11018250
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
  • Publication number: 20200357917
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 12, 2020
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
  • Patent number: 10593799
    Abstract: A semiconductor component includes a field-effect transistor arrangement having a drift zone and body region between the drift zone and a first surface of a semiconductor body. Trench structures of a first type extend from the first surface into the semiconductor body and have a maximum lateral dimension at the first surface which is less than a depth of first and second ones of the trench structures. A net doping concentration at a reference depth at a first location in the drift zone is at least 10% greater than at a second location in the drift zone at the reference depth, which is located between the body region and a bottom of the first trench structure. The first location is at the same first lateral distance from the first and second trench structures. The second location is at the same second lateral distance from the first and second trench structures.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Karl-Heinz Bach, Peter Brandl, Andrew Christopher Graeme Wood
  • Patent number: 10580656
    Abstract: A semiconductor wafer having a main surface is provided. A first etch resistant mask is provided on the main surface. A first reactive ion etching step that forms a first group of trenches using the first etch resistant mask is performed. Each of the trenches in the first group is covered with a second etch resistant mask after performing the first reactive ion etching step. A second reactive ion etching step that forms a second group of trenches using one or both of the first etch resistant mask and the second etch resistant mask is performed. The trenches in the second group are laterally offset from the trenches in the first group. The first and second reactive ion etching processes are performed such that a depth of the trenches of the first group is substantially equal to a depth of the trenches in the second group.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Marija Borna Tutuc, Daniel Tutuc, Andrew Christopher Graeme Wood
  • Patent number: 10535576
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 14, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Publication number: 20200013631
    Abstract: A semiconductor wafer having a main surface is provided. A first etch resistant mask is provided on the main surface. A first reactive ion etching step that forms a first group of trenches using the first etch resistant mask is performed. Each of the trenches in the first group is covered with a second etch resistant mask after performing the first reactive ion etching step. A second reactive ion etching step that forms a second group of trenches using one or both of the first etch resistant mask and the second etch resistant mask is performed. The trenches in the second group are laterally offset from the trenches in the first group. The first and second reactive ion etching processes are performed such that a depth of the trenches of the first group is substantially equal to a depth of the trenches in the second group.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 9, 2020
    Inventors: Marija Borna Tutuc, Daniel Tutuc, Andrew Christopher Graeme Wood
  • Publication number: 20190386133
    Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 19, 2019
    Inventors: Cristian Mihai Boianceanu, Liu Chen, Sebastian Sosin, Andrew Christopher Graeme Wood
  • Publication number: 20190334000
    Abstract: A transistor component includes at least one transistor cell having: a drift region, a source region, a body region and a drain region in a semiconductor body, the body region being arranged between the source and drift regions, and the drift region being arranged between the body and drain regions; a gate electrode arranged adjacent to the body region and dielectrically isolated from the body region by a gate dielectric; and a field electrode arranged adjacent to the drift region and dielectrically isolated from the drift region by a field electrode dielectric. The field electrode dielectric has a thickness that increases in a direction toward the drain region. The drift region has, in a mesa region adjacent to the field electrode, a doping concentration that increases in the direction toward the drain region.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 31, 2019
    Inventors: Markus Zundel, Karl-Heinz Bach, Peter Brandl, Franz Hirler, Andrew Christopher Graeme Wood
  • Patent number: 10453915
    Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Karl-Heinz Bach, Christian Kampen, Dietmar Kotz, Andrew Christopher Graeme Wood, Markus Zundel
  • Publication number: 20190051749
    Abstract: A semiconductor component includes a field-effect transistor arrangement having a drift zone and body region between the drift zone and a first surface of a semiconductor body. Trench structures of a first type extend from the first surface into the semiconductor body and have a maximum lateral dimension at the first surface which is less than a depth of first and second ones of the trench structures. A net doping concentration at a reference depth at a first location in the drift zone is at least 10% greater than at a second location in the drift zone at the reference depth, which is located between the body region and a bottom of the first trench structure. The first location is at the same first lateral distance from the first and second trench structures. The second location is at the same second lateral distance from the first and second trench structures.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 14, 2019
    Inventors: Markus Zundel, Karl-Heinz Bach, Peter Brandl, Andrew Christopher Graeme Wood
  • Publication number: 20180286944
    Abstract: A semiconductor device includes a semiconductor body having a semiconductor substrate of a first conductivity type and a semiconductor layer of the first conductivity type on the substrate. A trench structure extends into the semiconductor body from a first surface and includes a gate electrode and at least one field electrode arranged between the gate electrode and a bottom side of the trench structure. A body region adjoins the trench structure and laterally extends from a transistor cell area into an edge termination area. A pn junction is between the body region and semiconductor layer. A doping concentration of at least one of the body region and semiconductor layer is lowered at a lateral end of the pn junction in the edge termination area compared to a doping concentration of the at least one of the body region and semiconductor layer at the pn junction in the transistor cell area.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 4, 2018
    Inventors: Andreas Meiser, Karl-Heinz Bach, Christian Kampen, Dietmar Kotz, Andrew Christopher Graeme Wood, Markus Zundel
  • Patent number: 10090215
    Abstract: A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 2, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Patent number: 9917160
    Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andrew Christopher Graeme Wood, Oliver Blank, Martin Poelzl, Martin Vielemeyer
  • Publication number: 20180012819
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 11, 2018
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Patent number: 9847387
    Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 19, 2017
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Karl-Heinz Bach, Andrew Christopher Graeme Wood
  • Patent number: 9799583
    Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Krotscheck Ostermann, Andrew Christopher Graeme Wood, Peter Maier Brandl
  • Publication number: 20170125315
    Abstract: A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Patent number: 9583406
    Abstract: A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate. The method also includes forming a first array of contact pads disposed in the contact region. The method also includes forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher