Abstract: A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing units. The processor core is clocked by a clock signal. A branching instruction received by the central unit, in the course of a current cycle, is processed in the course of the current cycle.

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract: A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency checks between instructions supplied in the same machine cycle being effective in superscalar mode but disabled in very long instruction word mode.

Abstract: A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killed” later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.

Abstract: Instructions in a computer system are executed in a plurality of parallel execution pipelines, a horizontal dependency check is carried out between instructions supplied to the parallel pipelines and in response to detecting horizontal dependency a control signal of a first or second type is generated depending on whether the dependency can be resolved by activating a by-pass or whether a temporary stall is required in one of the pipelines.

Abstract: A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.

Abstract: A DRAM and its application to a mobile telephony circuit with a control circuit including a first refreshment controller controlled by a first clock signal and a second refreshment controller controlled by a second clock signal having a frequency less than that of the first one and used to synchronize events of the GSM network.

Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: A method of executing loops in a computer system is described. The computer system has a sequence of instructions held in program memory and a prefetch buffer which holds instructions fetched from the memory ready for supply to a decoder of the computer system. If the size of the loop to be executed is such that it can by holly contained within the prefetch buffer, this is detected and a lock is put on the prefetch buffer to retain the loop within it while the loop is executed a requisite number of times. This thus allows power to be saved and reduces the overhead on the memory access buffers. According to another aspect, loops can be “skipped” by holding a value of zero in the loop counter register.

Abstract: A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

Abstract: A cache memory is of the direct access type or of the set-associative type and includes NS sets each containing NW cache lines. NS is an integer greater than one, and NW is an integer equal to or greater than one. In the presence of a cache line access request, the content of the cache memory is scanned, the cache line is accessed if the latter is already allocated, and a new cache line is allocated in the cache memory in the contrary case. The cache memory is subdivided into SB subdivisions. Each subdivision includes NS/SB sub-sets each containing NW cache lines. Each subdivision is assigned a protection indication representative of whether or not the subdivision is protected. The scanning is carried out in all the subdivisions, whether protected or not. The access to a cache line already allocated is carried out even if that cache line belongs to a protected subdivision, whereas the allocation of a new cache line is carried out only in an unprotected subdivision.

Abstract: A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.