Abstract: A video processing device has an input for receiving video data, at least one processing circuit, for generating processed video data from the received video data, and a memory, for receiving the processed video data. An output circuit reads the processed video data from the memory, and generates frames of data including at least the processed video data. In order to be able to operate with an output clock frequency that may differ from the ideal output clock frequency, it is possible to vary the frame size, that is, the number of pixels of data in a frame. If an amount of processed video data stored in the memory exceeds an upper threshold, then the frame size can be reduced by reducing the number of pixels of blanking data in the output frame, thereby increasing the rate at which data is read from the memory.

Abstract: Methods and systems for memory interface systems are provided. A first command from control circuitry is received by bridge circuitry at a first clock rate. The control circuitry is configured to operate at the first clock rate. A second command is generated by the control circuitry on the received first command. The second command is transmitted to memory circuitry at a second clock rate. The memory circuitry is configured to operate at the second clock rate, and the second clock rate is greater than the first clock rate.

Abstract: Techniques and circuits for testing a memory are provided. The techniques include disabling a plurality of interrupts to an integrated circuit (IC). Contents of a first memory region to be tested are copied to a second memory region. The second memory region where the contents are copied to is a safe memory region that will not be affected by the memory test. Memory accesses are mapped to the second memory region so that memory accesses that are associated with the first memory region are mapped to the second memory region. The plurality of interrupts is re-enabled after the memory contents in the first memory region are copied and remapped to the second memory region. Memory accesses due to the interrupts are redirected from the first memory region to the second memory region according to the memory mapping. The first memory region is tested with a test circuit of the IC.

Abstract: Methods and apparatus are provided for handling reset events in a bus bridge. A system on a programmable chip includes master components and slave components supporting various bus protocols. Bus bridges allow components using different bus protocols to interact. Reset of a distinct subset of programmable chip components or the synchronization of reset signals across disparate clock domains is allowed by effectively handling reset related signals at a bus bridge.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: A microprocessor-based system includes multiple peripherals, which can be accessed by the microprocessor over a system bus, with the aid of address decoding logic. Depending on the required functionality of the system at any time, one or more of the peripherals can be disabled. When a peripheral device is disabled, the address decoding logic of the system is modified to ensure that no attempts are made to access that peripheral device.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced apart logic elements, and present the input signals to other logic elements, which, again, may be spaced apart throughout the device. Each of the distributed OR gates, and its connections to the other logic elements, acts as a multiplexer. Sufficient of these distributed OR gates are provided to allow a bus structure to be implemented within the device. Since the OR gates are provided separately from the logic elements of the programmable logic device, the required bus structure can be implemented more efficiently.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: A programmable logic device is provided with multiple power supplies such that, in one mode of operation, power can be disconnected from at least one part of the programmable logic device, while maintaining power at least to an interface component of the programmable logic device, or to a memory component in which current configuration data are stored, thereby avoiding the need for a configuration sequence when power is reapplied to the whole device. The programmable logic device may be provided as an integrated circuit, having multiple pairs of pins for connection to a supply voltage. Each of the pairs of pins provides power for a different subsection of the programmable logic device.

Abstract: A programmable logic device includes a gate array formed from programmable logic elements, and at least one address decoder structure. The address decoder has a first stage, for receiving bits of an address, and for masking out a first group of least significant bits of said address; a second stage, for comparing a second group of most significant bits of said address with respective comparison bits; and a third stage, for providing an output when all of the bits in said second group of bits of said address match their respective comparison bits. Thus, the address decoder can determine when a received address falls within a range of addresses associated with the address decoder. Multiple address decoders may be provided at spaced apart locations within the gate array, and one address decoder can be associated with each slave device implemented in the gate array. The programmable logic device may be used to implement a bus structure, with a bus master which may be in the form of an embedded processor.

Abstract: A direct memory access (DMA) controller is provided for a computer system having a processor and a command buffer. The command buffer can be defined, for example, as a ring buffer in the main processor memory and can be directly accessible by the processor, for example over a bus. The DMA controller provides a head register and a tail register operable to hold a head pointer and a tail pointer for addressing the head and tail, respectively, of a sequence of direct memory access commands in the command buffer. The processor is able to store DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. The DMA controller is operable to compare the head and tail pointers, and to respond to non-equivalence thereof to use the tail pointer value to access direct memory access commands from the command buffer.

Abstract: A bus bridge for a computer system for bridging first and second buses includes a shift and accumulate unit. The shift and accumulate unit includes a shifter having an input connected to receive bytes from one of the first and second buses and an output providing a selectable shift to the received bytes. The shift and accumulate unit also includes an accumulator having an input connected to receive the output of the shifter and providing accumulation of selectable bits of the shifted bytes, the accumulator having an output for supplying realigned bytes to be passed to the other of the first and second buses. The combination of the shifter and the accumulator permits a desired amount of shift to be combined with the accumulation of selected bits or bytes to realign sets of bytes from one bus and to form sets of bytes for the other bus. Burst transfer is also possible by operating the shift and accumulate unit to operate in successive cycles for successive sets of input bytes from one of the buses.