Abstract: A method and system for graphics instruction fetching. The method includes executing a plurality of threads in a multithreaded execution environment. A respective plurality of instructions are fetched to support the execution of the threads. During runtime, at least one instruction is prefetched for one of the threads to a prefetch buffer. The at least one instruction is accessed from the prefetch buffer if required by the one thread and discarded if not required by the one thread.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

Abstract: Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.

Abstract: A graphics processing subsystem includes a vertex processing unit that allows vertex shader programs to arbitrarily access data stored in vertex texture maps. The vertex processing unit includes a vertex texture fetch unit and vertex processing engines. The vertex processing engines operate in parallel to execute vertex shader programs that specify operations to be performed on vertices. In response to a vertex texture load instruction, a vertex processing engine dispatches a vertex texture request to the vertex texture fetch unit. The vertex texture fetch unit retrieves the corresponding vertex texture map data. While the vertex texture fetch unit is processing a vertex texture request, the requesting vertex processing engine is adapted to evaluate whether instructions that follow the vertex texture load instruction are dependent on the vertex texture map data, and if the instructions are not dependent on the vertex texture map data, to execute the additional instructions.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

Abstract: Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that improve utilization of storage buffers by overwriting data in them as soon as the data is no longer needed. An exemplary embodiment employs a counter to add each time a particular unit of data is needed by a circuit. The counter also subtracts each time the data is actually used by the circuit. When the counter reaches zero, upstream circuitry is checked to see if a command allowing the particular data to be overwritten has been issued. If it has, the command is not waited for, rather the data may be overwritten immediately. Embodiments of the present invention may also make use of one level of indirection to mask physical storage buffer locations from upstream circuitry. In this way, utilization can be improved.

Abstract: A method for tiling multiple displays to generate a large area display of moving data. Specifically, one embodiment of the present invention includes a system for generating a large area display of moving data. The system comprises a display image generator for rendering pixels of an image to be displayed as the large area display. Furthermore, a plurality of tiled image projectors are coupled to the display image generator to receive pixel data and to generate the large area display. The plurality of tiled image projectors comprise at least two image projectors. A first image projector which performs a first type of raster scanning sequence to display a first portion of the pixel data. Moreover, a second image projector which performs a second type of raster scanning sequence to display a second portion of the pixel data, wherein the second type of raster scanning sequence is different than the first type of raster scanning sequence.

Abstract: One aspect of the invention is a method for displaying extended range pixel values. The method includes the step of receiving a plurality of image pixel values each with at least one associated data value. The method also includes the steps of sending at least one of the plurality of image pixel values to a first display device (94) having a maximum display value; and sending at least one of the plurality of image pixel values exceeding maximum display value to a second display device (98). In a further embodiment, the at least one associated data value may be at least one of the group consisting of a pixel intensity, a color, and a location of the pixel value.

Abstract: A pull-model system and method provides display data over a network to a plurality of display devices having the same or different video format requirements. Utilization of image memory bandwidth is balanced between the plurality of display devices. Based on image memory bandwidth requirements for the plurality of display devices, a bandwidth allocation table is generated to indicate a servicing priority for the display devices. A plurality of requests for pixel data are received and stored in a request buffer. The requests are then serviced in an order indicated by the bandwidth allocation table.

Abstract: A method and apparatus for synchronizing the execution of a sequence of graphics pipelines is provided. For a representative embodiment a sequence of graphics pipelines are connected in a daisy-chain sequence. Each pipeline operation can be controlled to operated in one of two modes. The first is a local mode where the pipeline outputs its own digital video data. The second is a pass-through mode where the pipeline outputs digital video data received from preceding graphics pipelines. The pipelines are configured to allow an application executing on a host process to select the next pipeline that will enter local mode operation. The pipeline that is selected to enter local mode operation asserts a local ready signal when it is ready to begin outputting its digital video information. Each of the pipelines monitors the state of a global ready signal. When the global ready signal becomes asserted it means that the pipeline that is selected to enter local mode operation is ready.

Abstract: The present invention provides a method, a device, and a system for performing gamma correction on a set of pixel data based on a gamma correction curve table. The gamma correction curve table includes a specified total number of intensity levels associated with gamma corrected pixel values with one intensity level per pixel value. The method includes partitioning the gamma correction curve table into N segments such that each of the N segments is associated with a set of intensity levels from the specified total number of intensity levels. A plurality of intensity levels is selected for each of the N segments such that significant banding effects are not visible to the human eye between an adjacent pair of the selected intensity levels. The gamma corrected pixel values are stored for each of the N segments such that each of the plurality of selected intensity levels functions as an index to the associated gamma corrected pixel values.

Abstract: An addressing scheme for efficient memory use for storing textures with borders. Memory space is allocated for the texture maps, borders, and submaps equaled to two times the width times the height of the texture map to be stored. The memory space is then divided into a rectangular map space having a left-hand portion and a right-hand portion. Storage is accomplished by storing the main texture map on the left-hand portion of the map space. Submaps are then aligned along the bottom edge of the map space at the right in the right-hand portion. Finally, the borders are stored beginning at the top of the right-side portion of the rectangular space. The four corner edges of the borders are stored below the texel borders in the right-side portion.

Abstract: A system and method for determining and applying the effect of light polarization on the rendering of graphics objects. A polarization state buffer is provided to maintain polarization state on a pixel by pixel basis for each pixel in a frame buffer. As graphics objects are rendered the polarization state information is updated based on the underlying opaque surface, the polarization state of the light, and the characteristics of non-opaque objects being drawn. Pixel intensity is adjusted based on the degree of polarization, and the angle of the polarization axis. An approximation of the pixel intensity function is implemented using standard hardware logic.

Abstract: Hardware logic and processing methods for enhanced data manipulation within a graphics display system are described. The graphics display system includes a graphics processor sub-system and a rendering subsystem which are serially connected for pipeline processing of an interleaved stream of commands and data. One or more status bits or XBITs are defined within each rasterizer of a multi-rasterizer rendering sub-system. An XBIT, which may comprise a ZBIT, a UBIT, or an RBIT, etc., provides a mechanism for introducing execution of various logic functions within the rendering sub-system portion of the computer graphics adapter. Corresponding data processing methods are also described.

Abstract: A random access memory system organized such that multiple pixels may be accessed when one row column address is provided. The random access memory system includes a first group of random access memory devices and a second group of random access memory devices. The first group of devices stores information for pixels on an even horizontal scan line and the second group of devices stores information for pixels on an odd horizontal scan line. An address generator of the random access memory system generates an address to access information from the first group of devices for one pixel and information from the second group of devices for another pixel.

Abstract: An implementation of a flexible memory controller for a graphics hardware system that supports flexible allocation of frame buffer resources. The buffer selection and steering to the channels of the modification logic are performed by a programmable controller. Furthermore, the controller is capable of performing pixel functions that require multiple frame buffer accesses per pixel. Still further, independent control is provided for read and write sequences. Also, separate control is provided for buffer selection and bus steering. This function is useful for controlling systems where the frame buffer resources are limited. The present invention allows for assigning various buffers alternate functions based on the application's requirements, and may vary on a per window basis.

Abstract: A dynamic random access memory (DRAM) device that is selectively operable in a normal write mode, in a block write mode, or in a blocked flash write mode in accordance with a mode select signal. In the preferred embodiment, each column of a 512.times.512 DRAM is divided into eight superblocks of 64 columns, each superblock being in turn divided into eight blocks of 8 columns each. An address decoder decodes the most significant column address bits A8-A6 to provide a group select signal specifying a 64-bit superblock, the next most significant column address bits A5-A3 to provide a block select signal specifying a 8-bit block, and the least significant column address bits A2-A0 to provide a cell select signal specifying a particular column. In the normal write mode, data is written to the specified column in the specified block in the specified superblock. In the block write mode, the same data is simultaneously written to selected columns in the specified block in the specified superblock.

Abstract: The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port.