Abstract: Systems and methods for converting between a first color space format and a second color space format are described herein. The system receives a video cell in a first color space format comprising a plurality of pixels. Each pixel in the cell has a luminance value and a chrominance value. The luminance values of each pixel are compared to determine the brightest pixel in the received cell. The cell is downsampled to generate a second cell in a second color space format. The second cell in the second color space format comprises a downsampled chrominance value that is computed based at least in part on the chrominance value of the brightest pixel. The method advantageously reduces tinting of a high intensity pixel by the chrominance component of a neighboring low-intensity pixel.

Abstract: A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.

Abstract: A divider/multiplier circuit (10) is disclosed. In a divider mode, numerator terms are coupled to a normalizer (14) which generates normalized numerator values and corresponding numerator exponent values therefrom. Denominator terms are coupled to a look-up normalizer (20) which generates normalized denominator inverse values and corresponding denominator exponent values therefrom. The numerator and denominator exponent values are summed in an adder circuit (18) to generate a sum exponent value. The normalized numerator and inverse denominator values are multiplied in a multiplier circuit (16) to generate a normalized quotient value. The normalized quotient value is denormalized according to the sum exponent value. In a multiply mode of operation first and second multiplicands are coupled to the multiplier circuit (16). In a high precision divide mode, a sequence of numerator and inverse denominator values are coupled to the multiplier circuit (16) to generate a sequence of partial product terms.

Abstract: A method and apparatus of displaying video and graphics data together in a computer graphics display using only the memory needed for the graphics display includes determining the location of the video window in the frame buffer, writing video data to the portion of the frame buffer bounded by the video window. During the raster scan of the frame buffer, if the raster position is within the video window, video data are read from the video data addresses within the video window. When the displayed video window position is changed, the video data are moved accordingly.

Abstract: A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).

Abstract: A circuit and method for a display controller especially adapted for display memories organized in arrays. The invention permits high speed modification of the contents of a display by generating the address signals of a selected linear pattern as the data block to be modified is retrieved from the display memory. For vectors, the addresses are generated in the same time as required for data block retrieval. The invention also permits calculation of the addresses of simple curves as the data block to be modified is retrieved, though calculation times typically are longer than for vectors. Modified Breshenham's algorithm is used for the address calculation.