Patents by Inventor Andrew D. Huber
Andrew D. Huber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240135502Abstract: A neural network is trained and implemented to simultaneously remove noise and artifacts from medical images using a Generalized noise and Artifact Reduction Network (“GARNET”) method for training a convolutional neural network (“CNN”) or other suitable neural network or machine learning algorithm. Noise and artifact realizations from phantom images are used to synthetically corrupt images for training. Corrupted and uncorrupted image pairs are used for training GARNET. Following the training phase, GARNET can be used to improve image quality of routine medical images by way of noise and artifact reduction.Type: ApplicationFiled: February 14, 2022Publication date: April 25, 2024Inventors: Nathan R. Huber, Shuai Leng, Andrew D. Missert, Lifeng Yu, Cynthia H. McCollough
-
Patent number: 10759774Abstract: The present invention provides novel compounds and methods for treating, preventing or inhibiting hepatitis B virus (HBV).Type: GrantFiled: September 27, 2018Date of Patent: September 1, 2020Assignees: THE CURATORS OF THE UNIVERSITY OF MISSOURI, REGENTS OF THE UNIVERSITY OF MINNESOTAInventors: Stefan G. Sarafianos, Zhengqiang Wang, Andrew D. Huber, Jing Tang
-
Publication number: 20190092742Abstract: The present invention provides novel compounds and methods for treating, preventing or inhibiting hepatitis B virus (HBV).Type: ApplicationFiled: September 27, 2018Publication date: March 28, 2019Applicants: THE CURATORS OF THE UNIVERSITY OF MISSOURI, Regents of the University of MInnesotaInventors: Stefan G. Sarafianos, Zhengqiang Wang, Andrew D. Huber, Jing Tang
-
Patent number: 8938702Abstract: A mechanism is provided in a data processing system for timing-driven routing for noise reduction in integrated circuit design. Responsive to performing timing driving routing on an integrated circuit design, the mechanism identifies a set of noise-critical nets in the integrated circuit design. The mechanism performs timing driven routing on the integrated circuit design with noise constraints based on the set of noise-critical nets.Type: GrantFiled: December 19, 2013Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: Andre Hogan, Andrew D. Huber, Zhuo Li, Karsten Muuss, Sven Peyer, Christian Schulte, Gustavo E. Tellez
-
Patent number: 8631375Abstract: Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.Type: GrantFiled: April 10, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Robert R. Arelt, Jeanne P. S. Bickford, Andrew D. Huber, Gustavo E. Tellez, Karl W. Vinson, Tina Wagner
-
Publication number: 20130268908Abstract: Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.Type: ApplicationFiled: April 10, 2012Publication date: October 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert R. Arelt, Jeanne P. S. Bickford, Andrew D. Huber, Gustavo E. Tellez, Karl W. Vinson, Tina Wagner
-
Patent number: 8347257Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.Type: GrantFiled: June 8, 2010Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Taraneh E. Taghavi, Gustavo E. Tellez, Paul G. Villarrubia, Natarajan Viswanathan
-
Publication number: 20110302545Abstract: A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Jarrod A. Roy, Taraneh Taghavi, Gustavo E. Tellez, Paul G. Villarrubia, Natarajan Viswanathan
-
Patent number: 7496877Abstract: An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.Type: GrantFiled: August 11, 2005Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Andrew D. Huber, Ciaran J. Brennan, Paul E. Dunn, Scott W. Gould, Lin Lin, Erich C. Schanzenbach
-
Patent number: 6725439Abstract: A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.Type: GrantFiled: October 4, 2000Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Philip S. Homsinger, Andrew D. Huber, Debra K. Korejwa, William J. Livingstone, Jeannie H. Panner, Erich C. Schanzenbach, Douglas W. Stout, Steven H. Voldman, Paul S. Zuchowski
-
Patent number: 6493859Abstract: Disclosed is a method of routing power from a power network to one or more power service terminals within a voltage island, comprising: dividing the power network into segments; creating power service terminal to segment connections based on a first set of criteria; removing selected power service terminal to segment connections based on a second set of criteria; and selecting one power service terminal to segment connection for each the power service terminal. The first criteria is includes power drop, wire length, wire size, wiring layer restrictions and the second criteria includes electro-migration, wire length and current criteria.Type: GrantFiled: October 1, 2001Date of Patent: December 10, 2002Assignee: International Business Machines CorporationInventors: Scott W. Gould, Philip S. Honsinger, Andrew D. Huber, Patrick M. Ryan
-
Patent number: 5519632Abstract: A routing method for differential current switch (DCS) pairs initially shortens the min/max length window for a first routed rail in order to increase the likelihood that length of the second rail will fall within the window. Next, the routing domain for the first rail is modified so that the first pin exit direction to the route is toward the second pin of the differential current switch pair. A suitable algorithm, such as a prior art mazerouter algorithm, is used to route the first rail along a path restricted to the routing domain. At each proposed via connection for connecting the first rail route from one plane to another, the program accepts the proposed via connection only if there is an available adjacent via for routing the second via. If a via for routing the second rail is not available, the proposed route for the first rail is rejected.Type: GrantFiled: April 5, 1993Date of Patent: May 21, 1996Assignee: International Business Machines CorporationInventors: Hai H. Chen, Ling-Hui Hao, Philip S. Honsinger, Andrew D. Huber, Thomas J. Lavery, Shuhui Lin