Patents by Inventor Andrew D. Proescholdt
Andrew D. Proescholdt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11594522Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: GrantFiled: July 26, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Publication number: 20210351164Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Patent number: 11107795Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: GrantFiled: June 27, 2019Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Patent number: 10949300Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: GrantFiled: October 30, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20200073754Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: ApplicationFiled: October 30, 2019Publication date: March 5, 2020Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Patent number: 10496475Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: GrantFiled: July 9, 2018Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20190319013Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Patent number: 10388630Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: GrantFiled: December 1, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Publication number: 20180314593Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Patent number: 10067827Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: GrantFiled: June 29, 2016Date of Patent: September 4, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20180082983Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: ApplicationFiled: December 1, 2017Publication date: March 22, 2018Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Patent number: 9875993Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: GrantFiled: January 14, 2016Date of Patent: January 23, 2018Assignee: Micron Technology, Inc.Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Publication number: 20180004596Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Yihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Publication number: 20170207195Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.Type: ApplicationFiled: January 14, 2016Publication date: July 20, 2017Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
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Patent number: 6947328Abstract: A high-speed voltage level shifter. A transistor (10) may be connected to high voltage (VPP) and may act as a source of a limited current to a first node (21), and a driver (14, 15) connected to the first node may provide a level-shifted output signal (VOUT) to a memory control input line of a memory cell (6). A plurality of series-connected transistors (12A–12N) may be connected between a second node (22A) and a circuit ground, each transistor may have an input connected to a corresponding control signal (VIN-A to VIN-N) from a control circuit (5). A transistor (11) may be connected between the first node and the second node in a source-follower configuration and may have an input connected to a bias voltage (VBIAS) which may limit the voltage at node 22A, so transistors 12A–12N may be low-voltage, high speed transistors.Type: GrantFiled: December 29, 2003Date of Patent: September 20, 2005Assignee: Intel CorporationInventors: Alec W. Smidt, Andrew D. Proescholdt, Boubekeur Benhamida, Ravi Annavajjhala