Patents by Inventor Andrew David Habermas

Andrew David Habermas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180001439
    Abstract: The present disclosure includes barrier devices for use in an apparatus used to form lapping plates. The barrier devices can contain liquid on the surface of the lapping plate platen. The present disclosure also involves related methods.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Chea Phann, Ricky Ray Anderson, Kevin Lambert Mayer, Mihaela Ruxandra Baurceanu, Andrew David Habermas, Raymond Leroy Moudry, Joel William Hoehn
  • Publication number: 20170304988
    Abstract: The present disclosure involves a method of making a lapping plate by coating a platen with solid resin powder, abrasive particles, and an aqueous carrier followed by evaporating the aqueous carrier and curing the solid resin powder to form an abrasive coating. The present disclosure also involves related lapping plates.
    Type: Application
    Filed: April 20, 2016
    Publication date: October 26, 2017
    Inventors: Raymond Leroy Moudry, Mihaela Ruxandra Baurceanu, Joel William Hoehn, Andrew David Habermas
  • Publication number: 20170304989
    Abstract: The present disclosure involves a method of making a lapping plate by electrostatically coating a platen with solid resin powder and abrasive particles followed by curing the solid resin powder to form an abrasive coating. The present disclosure also involves related lapping plates.
    Type: Application
    Filed: April 20, 2016
    Publication date: October 26, 2017
    Inventors: Raymond Leroy Moudry, Mihaela Ruxandra Baurceanu, Joel William Hoehn, Andrew David Habermas
  • Patent number: 9343089
    Abstract: Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 17, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Andrew David Habermas, Dongsung Hong, Daniel Boyd Sullivan
  • Publication number: 20140254338
    Abstract: Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: Seagate Technology LLC
    Inventors: Andrew David Habermas, Dongsung Hong, Daniel Boyd Sullivan
  • Patent number: 8313659
    Abstract: A method for forming a multi-dimensional microstructure, such as but not limited to a three dimensional (3-D) microstructure coil for use in a data transducer of a data storage device. In accordance with some embodiments, the method generally includes providing a base region comprising a first conductive pathway embedded in a first dielectric material; etching a plurality of via regions in the first dielectric material that are each partially filled with a first seed layer that contacts the embedded first conductive pathway; and using the first seed layer to form a conductive pillar in each of the plurality of via regions, wherein each conductive pillar comprises a substantially vertical sidewall that extends to a first distance above the base region.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: November 20, 2012
    Assignee: Seagate Technology LLC
    Inventors: Helena Pavlovna Stadniychuk, Andrew David Habermas
  • Publication number: 20110008581
    Abstract: A method for forming a multi-dimensional microstructure, such as but not limited to a three dimensional (3-D) microstructure coil for use in a data transducer of a data storage device. In accordance with some embodiments, the method generally includes providing a base region comprising a first conductive pathway embedded in a first dielectric material; etching a plurality of via regions in the first dielectric material that are each partially filled with a first seed layer that contacts the embedded first conductive pathway; and using the first seed layer to form a conductive pillar in each of the plurality of via regions, wherein each conductive pillar comprises a substantially vertical sidewall that extends to a first distance above the base region.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 13, 2011
    Applicant: Seagate Technology LLC
    Inventors: Helena Pavlovna Stadniychuk, Andrew David Habermas