Abstract: Methods and systems for managing investments in a non-traded real estate investment trust or non-traded business development company are disclosed. One method includes receiving an identification of funds and investment instructions at a computing system from an investor, and automatically calculating commissions and fees based on the identification of funds and the investment instructions. The method also includes issuing shares to the investor based on a full value of the identified funds, investing the full value of the identified funds in an investment including in real estate or other assets, and automatically calculating a recurring fee for the investment.

Abstract: An integrated circuit includes first and second power supply voltage terminals, a voltage controlled oscillator (VCO), and a deep N-well field effect transistor (FET). The VCO has a first node coupled to the first power supply terminal, a second node, and first and second oscillator output terminals, at least one of which is coupled to a common pin. The deep N-well field-effect transistor (FET) has a first terminal coupled to the second node of the voltage controlled oscillator, a second terminal coupled to the second power supply terminal, and a control electrode to receive a power on signal, a deep N-well is coupled to the first power supply terminal and a P-channel is coupled to the second power supply terminal to form a high impedance electrostatic discharge path between the common pin and the first and the second power supply terminals through the deep N-well.

Abstract: A PM/FM modulator (100) includes an analog-to-digital converter (110) having an input terminal for receiving an analog input signal, and an output terminal, and a direct digital frequency synthesizer (120) having an input terminal coupled to the output terminal of the analog-to-digital converter, and an output terminal for providing a modulated output signal. In one form, an FM stereo modulator (200) includes a digital stereo modulator (210) and a direct digital frequency synthesizer (250). The digital stereo modulator (210) has a first input terminal for receiving a right analog input signal, a second input terminal for receiving a left analog input signal, and an output terminal for providing a digital signal having a stereo spectrum. The direct digital frequency synthesizer (250) has an input terminal coupled to the output terminal of the digital stereo modulator (210), and an output terminal for providing a modulated output signal.

Abstract: A receiver (200) includes a processing path (240), a plurality of power detectors (251, 252), and an automatic gain control circuit (250). The processing path (240) has an input for receiving an input signal, and an output for providing an output signal. Each of the plurality of power detectors (251, 252) has an input coupled to a different node of the processing path (240), and an output. The automatic gain control circuit (250) has inputs coupled to respective outputs of each of the plurality of power detectors (251, 252), and a first output adapted to be coupled to a first controllable gain element (241) for controlling a gain thereof in response to the outputs of the plurality of power detectors (251, 252).

Abstract: A technique includes applying a first gain to a first radio frequency signal to generate a second radio frequency signal, and the technique includes generating an intermediate frequency signal in response to the second radio frequency signal. In response to a change occurring in the first gain, a second gain that is applied to the intermediate frequency signal is changed to cancel at least some of the change in the first gain.

Abstract: A technique includes fabricating receive paths of a diversity receiver on a monolithic semiconductor die. The technique includes fabricating a local oscillator source on the die to be shared in common with the receive paths of the diversity receiver.

Abstract: A receiver (1100) includes a direct digital frequency synthesizer (130), a mixer (105), and a clock source (1110, 1130). The direct digital frequency synthesizer has an input terminal for receiving a first clock signal at a first frequency, and an output terminal for providing a digital local oscillator signal synchronously with the first clock signal. The mixer (105) has a first input terminal for receiving a radio frequency (RF) signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an IF signal having a spectrum centered about a selectable one of a plurality of center frequencies. The clock source (1110, 1130) has an output terminal for providing the first clock signal without using any harmonic frequency that overlaps the spectrum for any of the plurality of center frequencies.

Abstract: A transconductance amplifier (620) includes four transistors each operating in saturation and strong inversion. A first transistor (622) has a first current electrode and a control electrode both receiving an input voltage, and a second current electrode coupled to a power supply voltage terminal. A second transistor (624) has a first current electrode, a control electrode coupled to the first current electrode of the first transistor (622), and a second current electrode coupled to the power supply voltage terminal. A third transistor (626) has a first current electrode for providing a negative differential current, a control electrode for receiving a bias voltage, and a second current electrode coupled to the first current electrode of the first transistor (622).

Abstract: A mixer (114) includes an input amplifier (620) and a barrel shifter (640). The input amplifier (620) has an input for receiving an input signal, and first through fourth output terminals respectively providing first through fourth current signals. The barrel shifter (640) has first through fourth input terminals for respectively receiving the first through fourth current signals, first through fourth control terminals for respectively receiving first through fourth clock signals, and first through fourth output terminals for respectively providing positive and negative in-phase output signals and positive and negative quadrature output signals.

Abstract: A mixer (114) includes a phase clock generator (404), a latch (420), and a multiplier (118). The phase clock generator (404) provides a plurality of phase clock signals. The latch (420) is coupled to the phase clock generator (404) via a first plurality of conductors (410) and provides a plurality of resynchronized phase clock signals. The multiplier (118) is coupled to the latch (420) via a second plurality of conductors (430) and mixes an input signal using the plurality of resynchronized phase clock signals to provide a mixed output signal. The second plurality of conductors (430) is characterized as having a lower end-to-end impedance than an end-to-end impedance of the first plurality of conductors (410).

Abstract: A polyphase filter (320) includes first (340) and second (360) filter sections and a buffer section (350). The first filter section (340) has an input for receiving signals representative of at least two phases of an input signal, and an output for providing signals representative of at least two phases of a filtered signal, and has a first passband response. The buffer section (350) has an input coupled to the output of the first filter section (340), and an output. The second filter section (360) has an input coupled to the output of the buffer (350), and an output for providing an output of the polyphase filter (320), and has a second passband response. The first (340) and second (360) filter sections are configured such that the second passband response compensates for the first passband response.

Abstract: An antenna detection and diagnostic system and associated method, including current and voltage detection circuits, are disclosed for detecting antenna failure mechanisms for integrated radio receivers. Integrated current limit detection circuitry is disclosed that determines current levels drawn by a remotely mounted antenna and generates a drive signal that controls a current limiting pass transistor such that current flow through the transistor is reduced when the detected current level drawn antenna rises above a current limit level. Integrated current and voltage detection circuitry is disclosed that detects current and voltage levels drawn by a remotely mounted antenna and determines under-current, over-current, and over-voltage antenna error conditions. At least one antenna error output pin for the integrated radio receiver is then used provide an output signal indicative of antenna error conditions.

Abstract: An integrated circuit (500) includes a semiconductor substrate (400) and an integrated circuit package (530). The semiconductor substrate (400) has a first pair of bonding pads (442, 444) conducting a differential output signal thereon and adapted to be coupled to an input of a first external filter, and a second pair of bonding pads (452, 454) conducting a differential input signal thereon and adapted to be coupled to an output of said first external filter. The integrated circuit package (530) encapsulates the semiconductor substrate (400) and has first (452, 454) and second (552, 554) terminal pairs corresponding and coupled to the first (442, 444) and second (452, 454) pairs of bonding pads, respectively. The first (452, 454) and second (552, 554) terminal pairs are separated by a first predetermined distance is sufficient to maintain an input-to-output isolation therebetween of at least a first predetermined amount.

Abstract: Positions can be precisely and accurately fixed instantaneously within a three-dimensional workspace. A system of two or more transmitters each continuously sweep the workspace with two fanned laser beams which are preferably about 90 degrees apart on the rotational axis of the transmitter. A receiving instrument includes, preferably, two light detectors which detect the time at which each fanned laser beam is incident thereon. The light detectors also detect a synchronization pulse from each transmitter that is emitted once per revolution. Beams from different transmitters are differentiated by different rotational speeds and, therefore, different beam incidence cycles. Because three intersecting planes uniquely define a point in three-dimensional space, by detecting at least three of the fan beams from the transmitters, the receiving instrument can calculate its position in the workspace. A Quick Calc setup procedure allows the use to define a desired coordinate system within the workspace.

Abstract: A spatial measurement recovery system and method which determining the position, orientation, shape and/or operational characteristics of an environment. The system includes a data gathering apparatus and a model building apparatus. The data gathered may then be transformed into a CADD model of an as-built or as-is environment, or to otherwise map the environment in three dimensions.