Abstract: The invention relates to a feedback circuit for a transimpedance amplifier, which is typically used for converting an input current from a photodiode into an output voltage. The feedback circuit of the present invention linearizes the transconductance feedback, as the input current signal varies, by providing a constant current source for supplementing the DC feedback current through a bypass transistor, thereby reducing a variation in the low frequency cut off.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Abstract: A method and apparatus are provided for implementing dynamic noise immunity and minimizing delay of complementary metal oxide semiconductor (CMOS) logic circuits. A method of logical effort is applied to the CMOS logic circuits. Selected circuits within the CMOS logic circuits are checked for noise immunity utilizing a noise test simulation to identify each selected circuit failing the noise test simulation. An electrical effort is fixed to a value for providing noise immunity for each identified selected circuit failing the noise test simulation. The method of logical effort is applied to each remaining selected circuit not failing the noise test simulation. The sequential steps are repeated for each remaining selected circuit not failing the noise test simulation until no selected circuit failing the noise test simulation is identified. The selected circuits that are checked for noise immunity include, for example, dynamic circuits and passgate circuits.

Abstract: During scan testing of logical and memory circuits, it is important to prevent a scan test error resulting from simultaneous switching of the values within chip logic. Scan testing, however, encompasses rapidly scanning in values into a register to detect if the register is properly functioning. A circuit is disclosed which looks at the n−1 values within the register and determines if the next scan in value would cause contention. If so, that value is blocked until the next scan in value would not cause contention with the n−1 values within the register. Practicably, the invention will allow only allowed values into the register and may allow a “hot one” value into the register every n−1 clock cycle. Feedback of the values in the register is provided to a logical AND function to determine if a differing bit value will be allowed to scan into the register.

Abstract: A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal. The transistor stacks comprise silicon-on-insulator (SOI) transistors.

Abstract: A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.

Abstract: An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Abstract: A charge booster for a node in a dynamic logic circuit having a logic function evaluation network that includes a switching network and a dominant input switching device adapted to receive a plurality of input signals. In one aspect of the present invention, a precharge transistor is first turned on by a clock signal during a precharge phase to precharge the node that is coupled to an output of the dynamic logic circuit. Concurrently, during the precharge phase, an evaluate transistor is turned off. Next, during an evaluate phase, the evaluate transistor is turned on by the control signal, i.e., clock signal, permitting the logic function evaluation network to perform the predefined logic function in accordance with the input signals received by the logic function evaluation network. The logic function evaluation network selectively charges or discharges the node to a voltage level based on the predefined logic function.

Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Abstract: A method and apparatus for reducing bipolar current effects in dynamic logic circuits that are fabricated using the SOI technology is disclosed. A dynamic logic circuit capable of reducing bipolar current effects includes a precharge transistor (or a discharge transistor), a pass transistor, a functional logic circuit block, and an inverter. Connected in series with the precharge transistor, the functional logic circuit block, which includes multiple transistors, receives signal inputs. The pass transistor, connected in parallel with the precharge transistor, receives an identical input as one of the many transistors within the functional logic circuit block. The inverter, connected to a node between the precharge transistor and the functional logic circuit block, provides an output for the dynamic logic circuit.

Abstract: Logic functions using dual rail dynamic logic circuits are implemented by cross-coupling a pair shunt transistors to the outputs. Preferably, the precharge nodes provide input to the gates of respective inverter drivers, each inverter formed as a p-channel field-effect transistor (pFET) and an n-channel field-effect transistor (nFET). The circuit's logic functions discharge the precharge nodes to ground. Therefore, one of the precharge nodes discharges to ground, while the other retains its positive precharge. The inverter drivers drive the discharged precharge node high, while the precharge node which retains its original charge is driven low. The shunt transistors are nFETs which connect the outputs of the inverter drivers to ground. The gate of each shunt transistor is driven by the output of the opposite inverter driver. The output which is driven by a discharged precharge node is relatively immune from noise, since there is a path from the precharge node to ground through several open transistors.

Abstract: A method and apparatus for enhancing noise tolerance in dynamic Silicon-On-Insulator (SOI) logic gates improves the performance of dynamic gates using SOI technology. In particular implementations of logic, the logic inputs can be used to enable a pull-up chain constructed from a plurality of transistors. This pull-up chain holds the preset voltage on the summing node of the dynamic logic gate while the logic inputs are in a combination where parasitic bipolar transistors in the input logic chains conduct. The pull-up chain prevents spurious operation of the logic gate due to the conduction of the parasitic bipolar transistors. The pull-up also prevents spurious operation due to charge sharing that occurs when a device in the logic chain is enabled while another device is disabled. The charge sharing occurs due to charging the diffusion capacitance of the device which is disabled.

Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Abstract: In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.