Patents by Inventor Andrew du Preez
Andrew du Preez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140156888Abstract: An apparatus, method, and system embodying some aspects of the present embodiments for arbitrating communication between multiple communication devices are provided. The arbitration system include two communication devices and a packet traffic arbiter. The communication devices can be configured to receive or transmit data transmissions. The data transmissions can comprise protocol information. The protocol information can comprise transmission coordination information, handover information, and spectrum information. The packet traffic arbiter can be configured to coordinate the data transmissions between the two communication devices. The coordination can reduce traffic collisions or interference between low-power activities of the two communication devices.Type: ApplicationFiled: March 13, 2013Publication date: June 5, 2014Applicant: Broadcom CorporationInventor: Andrew du PREEZ
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Patent number: 8509698Abstract: Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.Type: GrantFiled: June 25, 2012Date of Patent: August 13, 2013Assignee: Broadcom CorporationInventors: Mark Hahm, Wei Luo, Thirunathan Sutharsan, Andrew du Preez, Bin Liu, Jun Wu, Severine Catreux-Erceg, Shuangquan Wang
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Patent number: 8503588Abstract: Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.Type: GrantFiled: November 3, 2009Date of Patent: August 6, 2013Assignee: Broadcom CorporationInventors: Wei Luo, Karthik Rajagopalan, Andrew du Preez, Bin Liu, Shuangquan Wang
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Patent number: 8429320Abstract: Aspects of a method and system for dynamically programmable serial/parallel bus interface may include performing in a first communication device coupled to a communication bus, attaching communication protocol information to a data signal for each data transaction with one or more other communication devices communicatively coupled to the communication bus. The one or more other communication devices may be controlled utilizing the attached communication protocol information. The communication protocol information may be dynamically adjusted and/or adaptively adjusted. The communication bus may be a serial or parallel communication bus. The serial communication bus may be a two-wire, three-wire, or four-wire bus. The attached communication protocol information comprises a multi-wire protocol, a 3-wire protocol, a Serial Peripheral Interface (SPI) protocol, a System Power Management Interface (SPMI), or an RF Bus protocol.Type: GrantFiled: April 7, 2010Date of Patent: April 23, 2013Assignee: Broadcom CorporationInventors: Andrew du Preez, Yi Zhou
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Publication number: 20120263030Abstract: Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.Type: ApplicationFiled: June 25, 2012Publication date: October 18, 2012Applicant: Broadcom CorporationInventors: Mark Hahm, Wei Luo, Thirunathan Sutharsan, Andrew du Preez, Bin Liu, Jun Wu, Severine Catreux-Erceg, Shuangquan Wang
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Patent number: 8208856Abstract: Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.Type: GrantFiled: January 13, 2010Date of Patent: June 26, 2012Assignee: Broadcom CorporationInventors: Mark Hahm, Wei Luo, Thirunathan Sutharsan, Andrew du Preez, Bin Liu, Jun Wu, Severine Catreux-Erceg, Shuangquan Wang
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Patent number: 8161217Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: GrantFiled: July 19, 2011Date of Patent: April 17, 2012Assignee: Broadcom CorporationInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Publication number: 20110276736Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: BROADCOM CORPORATIONInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Patent number: 7984216Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: GrantFiled: August 18, 2009Date of Patent: July 19, 2011Assignee: Broadcom CorporationInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Publication number: 20110151888Abstract: Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.Type: ApplicationFiled: January 13, 2010Publication date: June 23, 2011Inventors: Mark Hahm, Wei Luo, Thirunathan Sutharsan, Andrew du Preez, Bin Liu, Jun Wu, Severine Catreux-Erceg, Shuangquan Wang
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Publication number: 20110153887Abstract: Aspects of a method and system for dynamically programmable serial/parallel bus interface may include performing in a first communication device coupled to a communication bus, attaching communication protocol information to a data signal for each data transaction with one or more other communication devices communicatively coupled to the communication bus. The one or more other communication devices may be controlled utilizing the attached communication protocol information. The communication protocol information may be dynamically adjusted and/or adaptively adjusted. The communication bus may be a serial or parallel communication bus. The serial communication bus may be a two-wire, three-wire, or four-wire bus. The attached communication protocol information comprises a multi-wire protocol, a 3-wire protocol, a Serial Peripheral Interface (SPI) protocol, a System Power Management Interface (SPMI), or an RF Bus protocol.Type: ApplicationFiled: April 7, 2010Publication date: June 23, 2011Inventors: Andrew du Preez, Yi Zhou
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Patent number: 7949012Abstract: A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE) is provided. This combined cipher multiplexing engine includes a master port, a radio link control (RLC) data packer, and a cipher multiplexing processing module. The master port couples to an advanced microprocessor bus architecture (AMBA) high speed buss (AHB) on which control information for the combined cipher and multiplexing engine is provided. The RLC couples to the master port and receives RLC service data units (SDUs) from the AHB. Then the RLC data packer may concatenate or segment RLC SDUs into RLC packet data units (PDUs) which are stored for use by a cipher multiplexing processing module.Type: GrantFiled: September 26, 2007Date of Patent: May 24, 2011Assignee: Broadcom CorporationInventors: Li Fung Chang, Andrew Du Preez
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Publication number: 20110103530Abstract: Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.Type: ApplicationFiled: November 3, 2009Publication date: May 5, 2011Inventors: Wei Luo, Karthik Rajagopalan, Andrew du Preez, Bin Liu, Shuangquan Wang
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Publication number: 20090307402Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: ApplicationFiled: August 18, 2009Publication date: December 10, 2009Applicant: BROADCOM CORPORATIONInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Patent number: 7577779Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.Type: GrantFiled: February 14, 2006Date of Patent: August 18, 2009Assignee: Broadcom CorporationInventors: Frederic Hayem, Andrew du Preez, Louis Botha, Johan (Hendrik) Conroy
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Publication number: 20090034507Abstract: A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE) is provided. This combined cipher multiplexing engine includes a master port, a radio link control (RLC) data packer, and a cipher multiplexing processing module. The master port couples to an advanced microprocessor bus architecture (AMBA) high speed buss (AHB) on which control information for the combined cipher and multiplexing engine is provided. The RLC couples to the master port and receives RLC service data units (SDUs) from the AHB. Then the RLC data packer may concatenate or segment RLC SDUs into RLC packet data units (PDUs) which are stored for use by a cipher multiplexing processing module.Type: ApplicationFiled: September 26, 2007Publication date: February 5, 2009Applicant: BROADCOM CORPORATIONInventors: Li Fung Chang, Andrew Du Preez