Abstract: A one-time programmable memory device includes a first doped region in a semiconductor substrate, a second doped region implanted within the first doped region, and a gate positioned over the second doped region. The first doped region and second doped regions form a diode. A first contact is coupled to the first doped region for applying a voltage to the first doped region. The gate includes a dielectric portion that is capacitively coupled to the second doped region. The gate also includes a conductive portion that is coupled to a second contact for applying a voltage to the conductive portion. The voltage applied to the conductive portion is independent from the voltage applied to the first doped region. The memory device is programmed by forming a rupture in the dielectric portion of the gate.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A drain region and a source region of an opposite polarity are also in the semiconductor substrate. The drain region is positioned over the first, higher doped region, and the drain is positioned over the second, lower doped region. The select device above the semiconductor substrate can form a channel in a channel region of the semiconductor substrate between the source region and the drain region. One portion of the select device is positioned over the first, lower doped region, and another portion of the select device is positioned over the second, higher doped region. An anti-fuse device is positioned above the second doped region and in part above a portion of the source region.

Abstract: A one-time programmable memory device includes a well of a first polarity in a semiconductor substrate. A lightly-doped drain (LDD) region is above one portion of the well. The LDD region has a first doping concentration and a second polarity that is opposite the first polarity. A source region or a drain region of the second polarity is above another portion of the well. The source region or the drain region has a second doping concentration that is higher than the first doping concentration. A first breakdown voltage between the LDD region and the well region is higher than a second breakdown voltage between the source region or the drain region and the well region. A select device is positioned at least partially above a portion of the source region or the drain region. The select device is configured to form a channel between the source region or the drain region and the LDD region. An anti-fuse device is positioned at least partially above a portion of the LDD region.

Abstract: An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.

Abstract: A one-time programmable memory device includes a well of a first polarity in a semiconductor substrate. A lightly-doped drain (LDD) region is above one portion of the well. The LDD region has a first doping concentration and a second polarity that is opposite the first polarity. A source region or a drain region of the second polarity is above another portion of the well. The source region or the drain region has a second doping concentration that is higher than the first doping concentration. A first breakdown voltage between the LDD region and the well region is higher than a second breakdown voltage between the source region or the drain region and the well region. A select device is positioned at least partially above a portion of the source region or the drain region. The select device is configured to form a channel between the source region or the drain region and the LDD region. An anti-fuse device is positioned at least partially above a portion of the LDD region.

Abstract: Embodiments relate to an anti-fuse device with a transistor. The transistor may be a FinFET. The anti-fuse device includes a first electrode, an insulating layer, and a second electrode. The gate of the transistor may be formed in a same layer as the first electrode. The gate insulating layer on the gate of the transistor may be formed in a same layer as the insulating layer. The second electrode may be formed in a same layer as a local interconnect or a via and overlap the first electrode vertically over the insulating layer.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a source and a drain formed in an active region of a substrate and separated by a channel region in the active region. A gate stack formed over the substrate includes a gate formed on an oxide and at least one sidewall spacer formed around the gate. A charge trapping layer is formed on an opposite side of the sidewall spacer from the gate, where at least a portion of the charge trapping layer acts as a floating gate for the bitcell. The bitcell further includes a salicide block covering the floating gate portion of the charge trapping layer. An contact (sometimes referred to as a bar contact) physically contacts the salicide block above the floating gate portion of the charge trapping layer.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a source and a drain formed in an active region of a substrate and separated by a channel region in the active region. A gate stack formed over the substrate includes a gate formed on an oxide and at least one sidewall spacer formed around the gate. A charge trapping layer is formed on an opposite side of the sidewall spacer from the gate, where at least a portion of the charge trapping layer acts as a floating gate for the bitcell. The bitcell further includes a salicide block covering the floating gate portion of the charge trapping layer. An contact (sometimes referred to as a bar contact) physically contacts the salicide block above the floating gate portion of the charge trapping layer.

Abstract: An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a gated diode device. The capacitor, transistor, and gated diode device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The gated diode device allows for erasure of an entire NVM memory more efficiently and using less substrate space than a similar device that uses a transistor. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.

Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.