Patents by Inventor Andrew E. Oishei

Andrew E. Oishei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9582628
    Abstract: A method for designing a power distribution network (PDN) for a system implementing a target device includes computing a target PDN impedance value for the PDN. For each switching frequency of the target device where an effective PDN impedance value for the PDN is greater than the target PDN impedance value, one or more decoupling capacitors for one or more capacitor types are identified to add to the PDN to drive the effective PDN impedance value below the target PDN value. A selection of decoupling capacitors identified is refined to reduce one or more of a cost of the PDN and space required for implementing the PDN.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: February 28, 2017
    Assignee: Altera Corporation
    Inventors: Andrew E. Oishei, Dmitry Denisenko
  • Patent number: 8627261
    Abstract: A method for designing a power distribution network (PDN) for a system implementing a target device includes computing a target PDN impedance value for the PDN. For each switching frequency of the target device where an effective PDN impedance value for the PDN is greater than the target PDN impedance value, one or more decoupling capacitors for one or more capacitor types are identified to add to the PDN to drive the effective PDN impedance value below the target PDN value. A selection of decoupling capacitors identified is refined to reduce one or more of a cost of the PDN and space required for implementing the PDN.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: January 7, 2014
    Assignee: Altera Corporation
    Inventors: Andrew E. Oishei, Dmitry Denisenko
  • Patent number: 8332790
    Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: December 11, 2012
    Assignee: Altera Corporation
    Inventors: Andrew E. Oishei, Gregory Moore
  • Patent number: 7818704
    Abstract: The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: October 19, 2010
    Assignee: Altera Corporation
    Inventors: Andrew E. Oishei, Gregory Moore