Patents by Inventor Andrew Edmund Turner
Andrew Edmund Turner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359373Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Engin Ipek, Hamza Omar, Bohuslav Rychlik, Saumya Ranjan Kuanr, Behnam Dashtipour, Michael Hawjing Lo, Jeffrey Gemar, Matthew Severson, George Patsilaras, Andrew Edmund Turner
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Patent number: 11681624Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.Type: GrantFiled: July 17, 2020Date of Patent: June 20, 2023Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Bohuslav Rychlik, George Patsilaras
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Patent number: 11636625Abstract: Embodiments include methods for image compression and decompression. A sending computing device may determine a type of packing used for a chunk of image data, generate metadata describing the type of packing used for the chunk of image data, pack the chunk of image data according to the determined type of packing, and send the packed chunk of image data and the metadata to a second computing device. A receiving computing device may decode the metadata describing the type of packing used for the chunk of image data, determine the type of packing used for the chunk of image data based on the decoded metadata, and unpack the chunk of image data according to the determined type of packing used for the chunk of image data.Type: GrantFiled: December 11, 2020Date of Patent: April 25, 2023Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Prashant Dinkar Karandikar
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Patent number: 11599468Abstract: Memory system features may promote cache coherency where first and second memory clients may attempt to work on the same data. A second client cache system may provide a read request for data and associated metadata. The metadata element may be detected in a first client cache system. The first client cache system may write or flush, such as to a system memory, one or more cache lines containing the metadata and associated data and invalidate the flushed cache lines. The second client cache system may receive the data and metadata, such as from the system memory, completing or fulfilling the read request.Type: GrantFiled: November 30, 2021Date of Patent: March 7, 2023Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, George Patsilaras
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Publication number: 20220189068Abstract: Embodiments include methods for image compression and decompression. A sending computing device may determine a type of packing used for a chunk of image data, generate metadata describing the type of packing used for the chunk of image data, pack the chunk of image data according to the determined type of packing, and send the packed chunk of image data and the metadata to a second computing device. A receiving computing device may decode the metadata describing the type of packing used for the chunk of image data, determine the type of packing used for the chunk of image data based on the decoded metadata, and unpack the chunk of image data according to the determined type of packing used for the chunk of image data.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Inventors: Andrew Edmund TURNER, Prashant Dinkar KARANDIKAR
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Publication number: 20220113901Abstract: Various embodiments include methods and devices for managing optional commands. Some embodiments may include receiving an optional command from an optional command request device, determining whether the optional command can be implemented, and transmitting, to the optional command request device, an optional command no data response in response to determining that the optional command cannot be implemented.Type: ApplicationFiled: October 12, 2020Publication date: April 14, 2022Inventors: Andrew Edmund TURNER, George PATSILARAS, Zhenbiao MA, Subbarao PALACHARLA, Bohuslav RYCHLIK, Tarek ZGHAL, Christopher KOOB
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Publication number: 20220019534Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.Type: ApplicationFiled: July 17, 2020Publication date: January 20, 2022Inventors: Andrew Edmund Turner, Bohuslav Rychlik, George Patsilaras
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Publication number: 20210200679Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.Type: ApplicationFiled: March 17, 2021Publication date: July 1, 2021Inventors: Andrew Edmund TURNER, George PATSILARAS, Bohuslav RYCHLIK, Wesley James HOLLAND, Jeffrey SHABEL, Simon Peter William BOOTH
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Patent number: 11016898Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.Type: GrantFiled: August 16, 2019Date of Patent: May 25, 2021Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, George Patsilaras, Bohuslav Rychlik, Wesley James Holland, Jeffrey Shabel, Simon Peter William Booth
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Publication number: 20210049099Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.Type: ApplicationFiled: August 16, 2019Publication date: February 18, 2021Inventors: ANDREW EDMUND TURNER, George PATSILARAS, Bohuslav RYCHLIK, Wesley James HOLLAND, Jeffrey SHABEL, Simon Peter William BOOTH
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Patent number: 10747671Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.Type: GrantFiled: February 6, 2019Date of Patent: August 18, 2020Assignee: QUALCOMM IncorporatedInventors: Wesley James Holland, Bohuslav Rychlik, Andrew Edmund Turner, George Patsilaras, Jeffrey Shabel, Simon Peter William Booth
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Publication number: 20200250101Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Inventors: GEORGE PATSILARAS, Wesley James Holland, Bohuslav Rychlik, Andrew Edmund Turner, Jeffrey Shabel, Simon Peter William Booth, Simo Petteri Kangaslampi, Christopher Koob, Wisnu Wurjantara, David Hansen, Ron Lieberman, Daniel Palermo, Colin Sharp, Hao Liu
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Publication number: 20200250097Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Inventors: WESLEY JAMES HOLLAND, Bohuslav Rychlik, Andrew Edmund Turner, George Patsilaras, Jeffrey Shabel, Simon Peter William Booth
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Patent number: 10503643Abstract: Systems and methods for managing coherency in a processing system comprising a memory involve one or more aperture cache coherency (ACC) blocks. The ACC blocks monitor accesses to the memory using aliased addresses, wherein the aliased addresses map to locations in an aliased address domain of the memory. The ACC blocks also monitor accesses to the memory through a functional address aperture using aperture addresses, wherein a function of the aperture addresses map to locations in an aperture address domain of the memory. The ACC blocks are further configured to maintain coherency between one or more of data in a first location of the memory, the first location belonging to the aliased address domain and the aperture address domain; one or more copies of the data accessed using the aperture addresses; or one or more copies of the data accessed using the aliased addresses.Type: GrantFiled: July 11, 2018Date of Patent: December 10, 2019Assignee: Qualcomm IncorporatedInventors: Bohuslav Rychlik, Wesley James Holland, Hao Liu, Andrew Edmund Turner
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Patent number: 10339058Abstract: Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.Type: GrantFiled: July 25, 2017Date of Patent: July 2, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Farrukh Hijaz, Bohuslav Rychlik
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Patent number: 10261910Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.Type: GrantFiled: March 22, 2016Date of Patent: April 16, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, George Patsilaras, Bohuslav Rychlik
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Patent number: 10255181Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.Type: GrantFiled: September 19, 2016Date of Patent: April 9, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Bohuslav Rychlik
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Patent number: 10248565Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.Type: GrantFiled: September 19, 2016Date of Patent: April 2, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Edmund Turner, Bohuslav Rychlik
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Patent number: 10157139Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing asynchronous cache maintenance operations on a computing device, including activating a first asynchronous cache maintenance operation, determining whether an active address of a memory access request to a cache is in a first range of addresses of the first active asynchronous cache maintenance operation, and queuing the first active asynchronous cache maintenance operation as the first asynchronous cache maintenance operation in a fixup queue in response to determining that the active address is in the first range of addresses.Type: GrantFiled: September 19, 2016Date of Patent: December 18, 2018Assignee: QUALCOMM IncorporatedInventor: Andrew Edmund Turner
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Publication number: 20180336133Abstract: Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.Type: ApplicationFiled: July 25, 2017Publication date: November 22, 2018Inventors: Andrew Edmund TURNER, Farrukh HIJAZ, Bohuslav RYCHLIK