Abstract: Certain exemplary embodiments can be used to implement a method, system, device, software program product, machine-readable medium, signal, and/or user interface for, among other things: automatically down-sampling a first version of a digital image product to a second version; automatically uploading or downloading a predetermined version of the digital image product; automatically applying a transformation to a predetermined version of the digital image product; and/or automatically synchronizing versions across a server and/or multiple clients.

Abstract: An automated process of conducting an online sweepstakes and marketing to sweepstakes entrants. The software system enables a non-technical individual (e.g., sweepstakes manager, marketer, etc.) to create a sweepstakes entry form that is integrated with back-end data processing systems. The entry form and entry form processing system are kept consistent with sweepstakes rules chosen by the non-technical individual and automatically generated by the system. The system enforces compliance with applicable laws with integrated tools to pick winners, to determine eligibility and to collect winner affidavits. A back-end database is integrated directly with a sweepstakes entry form. Online tools permit a marketer to view entrants and select entrants to receive direct email. Direct-email marketing tools are integrated with the sweepstakes front-end system, which allows a marketer to send out promotional offers and business communications directly from the sweepstakes system.

Abstract: In a computer system having a number of nodes, wherein one of the nodes has a number of processors which share a single cache, a method of providing release consistent memory coherency. Initially, a write stream is divided into separate intervals or epochs at each cache, delineated by processor synch operations. When a write miss is detected, a counter corresponding to the current epoch is incremented. When the write miss globally completes, the same epoch counter is decremented. Synch operations issued to the cache stall the issuing processor until all epochs up to and including the epoch that the synch ended have no misses outstanding. Write cache misses complete from the standpoint of the cache when ownership and data are present. This allows the latency of writes operations to be partially hidden in any combination of shared cache (both hardware and software controlled), and multiple context processors.