Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may determine whether to divide a group of threads into a plurality of sub-groups of threads, each thread of the group of threads being associated with a shader program. The apparatus may also divide, upon determining to divide the group of threads into the plurality of sub-groups of threads, the group of threads into the plurality of sub-groups of threads. Additionally, the apparatus may execute, upon dividing the group of threads into the plurality of sub-groups of threads, a subsection of the shader program for each sub-group of threads of the plurality of sub-groups of threads.

Abstract: The present disclosure relates to methods and apparatus for configuring a texture filtering logic unit for deep learning operation. The apparatus can map one or more inputs of a deep learning operation to a respective input of a texture filtering logic unit in a graphics pipeline. Moreover, the apparatus can generate, by the texture filtering logic unit, at least one output for the deep learning operation based on the one or more inputs mapped to the texture filtering logic unit. Furthermore, the apparatus can communicate the at least one output to a programmable shader, which can analyze the output result to determine information relating to an input image based on the deep learning operation.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may modify at least one texture memory object to support a data structure for one or more tensor objects. The apparatus may also determine one or more supported memory layouts for the one or more tensor objects based on the modified at least one texture memory object. Additionally, the apparatus may access data associated with the one or more tensor objects based on the one or more supported memory layouts, the data for each of the one or more tensor objects corresponding to at least one data instruction. The apparatus may also execute the at least one data instruction based on the accessed data associated with the one or more tensor objects.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.

Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, the apparatus selects a first mip-map layer with a first texture size and a second mip-map layer with a second texture size based on a third texture size of an image. The apparatus also determines a relative distance associated with the texture sizes. Additionally, the apparatus determines a first quantity of samples to select from the first mip-map layer, and determines a second quantity of samples to select from the second mip-map layer, the second quantity of samples being less than the first quantity of samples, and a second quantity of filter taps being less than a first quantity of filter taps. Also, the apparatus generates the image at the third texture size through filtering based on the first quantity of samples and the second quantity of samples.

Abstract: The present disclosure relates to methods and apparatus for mapping a source location of input data for processing by a graphics processing unit. The apparatus can configure a processing element of the graphics processing unit with a predefined rule for decoding a data source parameter for executing a task by the graphics processing unit. Moreover, the apparatus can store the parameter in local storage of the processing element and configure the processing element to decode the parameter according to the at least one predefined rule to determine a source location of the input data and at least one relationship between invocations of the task. The apparatus can also load, to the local storage of the processing element, the input data from a plurality of memory addresses of the source location determined by the parameter. A one logic unit can then execute the task on the loaded input data.

Abstract: The present disclosure relates to methods and apparatus for configuring a texture filtering logic unit for deep learning operation. The apparatus can map one or more inputs of a deep learning operation to a respective input of a texture filtering logic unit in a graphics pipeline. Moreover, the apparatus can generate, by the texture filtering logic unit, at least one output for the deep learning operation based on the one or more inputs mapped to the texture filtering logic unit. Furthermore, the apparatus can communicate the at least one output to a programmable shader, which can analyze the output result to determine information relating to an input image based on the deep learning operation.

Abstract: A graphics processing unit (GPU) utilizes block general purpose registers (bGPRs) to load multiple waves of samples for an instruction group into a processing pipeline and receive processed samples from the pipeline. The GPU acquires a credit for the bGPR for execution of the instruction group for a first wave using a persistent GPR and the bGPR. The GPU refunds the credit upon loading the first wave into the pipeline. The GPU executes a subsequent wave for the instruction group to load samples to the pipeline when at least one credit is available and the pipeline is processing the first wave. The GPU stores an indication of each wave that has been loaded into the pipeline in a queue. The GPU returns samples for a next wave in the queue from the pipeline to the bGPR for further processing when the physical slot of the bGPR is available.

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for GPR optimization in a GPU based on a GPR release mechanism. More specifically, a GPU may determine at least one unutilized branch within an executable shader based on constants defined for the executable shader. Based on the at least one unutilized branch, the GPU may further determine a number of GPRs that can be deallocated from previously allocated GPRs. The GPU may deallocate, for a subsequent thread within a draw call, the number of GPRs from the previously allocated GPRs during execution of the executable shader based on the determined number of GPRs to be deallocated.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.

Abstract: Methods, systems, and devices for graphic processing are described. The methods, systems, and devices may include or be associated with identifying a graphics instruction, determining that the graphics instruction is alias enabled for the device, partitioning an alias lookup table into one or more slots, allocating a slot of the alias lookup table based on the partitioning and determining that the graphics instruction is alias enabled, generating an alias instruction based on allocating the slot of the alias lookup table and determining that the graphics instruction is alias enabled, and processing the alias instruction.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. The present disclosure can calculate a center-edge distance of a first pixel, the center-edge distance of the first pixel equal to a distance from a first pixel center to one or more edges of a first primitive. Additionally, the present disclosure can store the center-edge distance of the first pixel when the first primitive is visible in a scene. The present disclosure can also determine an amount of overlap between the first pixel and the first primitive. Further, the present disclosure can blend a color of the first pixel with a color of a second pixel based on at least one of the center-edge distance of the first pixel or the amount of overlap between the first pixel and the first primitive.