Abstract: A method of filling features of a substrate to produce a planar patterned surface on said substrate is disclosed. The method includes the steps of: providing a substrate containing a pattern of features defined by a dielectric material; depositing thereon a layer of a conductor, whereby first portions of the conductive layer cover the dielectric material, second portions of the conductor layer fill the features, and third sidewall portions of the conductive layer connect the first and second portions; coating the substrate with a resist and patterning the resist with a resist pattern similar to said pattern of features; etching away all portions of the conductor layer, except the second portions filling the features, by etching under conditions such that lateral etching of the sidewall portions of the conductor layer is inhibited; and stripping the resist to result in a substrate having a substantially planar patterned surface. Planarized multichip modules and integrated circuits are also disclosed.