Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

Abstract: Example methods, apparatus, systems for droplet actuator fabrication are disclosed. An example non-transitory computer readable medium includes instructions that, when executed, cause at least one processor to at least control movement of a laser to cause the laser to etch an electrode pattern in a first substrate, the electrode pattern including a first set of electrodes, a second set of electrodes, and a third set of electrodes; control a printer driver to cause a hydrophobic material and a dielectric material to be applied to the second set of electrodes and not the first set of electrodes via a printer; control a bonding driver to cause a gap to be defined between the first substrate and a second substrate; and control a dicing driver to cause a portion the first substrate and a portion of the second substrate to be cut into a droplet actuator.

Abstract: A plastic container includes a base, an opening, and a plurality of panels. In embodiments, the plurality of panels are configured for digital printing. Systems and methods for digital printing on plastic containers with a plurality of panels are also disclosed.

Abstract: A plastic container assembly includes an outer container and an inner liner or bag, wherein the inner liner or bag is expanded within the outer container. Processes for making a plastic container with an inner liner are also disclosed.

Abstract: A plastic container includes a base, an opening, and a plurality of panels. In embodiments, the plurality of panels are configured for digital printing. Systems and methods for digital printing on plastic containers with a plurality of panels are also disclosed.

Abstract: The disclosed embodiments relate to a computer-based system and/or method which automatically, e.g. with minimal, or entirely without, human intervention, identifies, distinguishes, disambiguates or otherwise differentiates among multiple configurable bicycles based on the data reported to the system from the bicycle's data-reporting components, such that the data reported by those components may be associated with a particular bicycle for real-time and/or later review, analysis, etc. More particularly, where one or more data reporting components of a bicycle may change, the disclosed embodiments enable a data gathering system/service to identify, distinguish, disambiguate or otherwise differentiate among multiple bicycles which may use, or have used, one or more of the same components so as to associate the reported data, such as from a particular ride, with the correct bicycle configuration for real-time and/or later review and/or analysis.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

Abstract: A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

Abstract: Integrated devices that include a sample preparation component integrated with a detection component are disclosed. The sample preparation component may be a digital microfluidics module or a surface acoustic wave module which modules are used for combing a sample droplet with a reagent droplet and for performing additional sample preparation step leading to a droplet that contains beads/particles/labels that indicate presence or absence of an analyte of interest in the sample. The beads/particles/labels may be detected by moving the droplet to the detection component of the device, which detection component includes an array of wells.

Abstract: A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware device

Abstract: Embodiments of a multithreaded processor and a method of assigning blocks of register files for hardware threads of multithreaded processors are disclosed.

Abstract: Embodiments of a multithreaded processor and a method of assigning blocks of register files for hardware threads of multithreaded processors are disclosed.

Abstract: A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

Abstract: A mold assembly for manufacturing molded articles includes a plurality of mold portions that are comprised of a polymer and form a mold cavity. In embodiments, the polymer has a thermal conductivity (k) of less than about 0.5. Although, some embodiments may have higher conductivity values. In embodiments, the polymer comprises polycarbonate. Methods for making and using polymer mold portions and assemblies are also disclosed.

Abstract: An enhanced security of multiple software processes executing on a computer system is provided by isolating those processes from each other and from access to system hardware resources. Embodiments provide such isolation by executing kernel software that manages hardware and controls physical address space on a separate hardware thread (e.g., in an isolation domain) from the process threads executing application programs (e.g., in execution domains). This renders the software executing in the isolation domain safe from privilege escalation attacks and permits implementation of enforceable isolation between execution systems. A multithreaded processor having switch-on-event multithreading is used to provide software isolation and hardware-controlled handling of a subset of system services by a different hardware thread than the one requesting the service.

Abstract: A processing system includes a system interconnect, a processor coupled to communicate with other components in the processing system through the system interconnect, distributed general purpose registers (GPRs) in the processing system wherein a first subset of the distributed GPRs is located in the processor and a second subset of the distributed GPRs is located in the processing system and external to the processor, and a first set of conductors directly connected between the processor and the second subsets of the distributed GPRs. An instruction execution pipeline in the processor accesses any register in the first and second subsets of the distributed GPRs as part of the processor's GPRs during instruction execution in the processor, in which the second subset of the distributed GPRs is accessed through the first conductor.

Abstract: Integrated devices that include a sample preparation component integrated with a detection component are disclosed. The sample preparation component may be a digital microfluidics module or a surface acoustic wave module which modules are used for combing a sample droplet with a reagent droplet and for performing additional sample preparation step leading to a droplet that contains beads/particles/labels that indicate presence or absence of an analyte of interest in the sample. The beads/particles/labels may be detected by moving the droplet to the detection component of the device, which detection component includes an array of wells.

Abstract: A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware device

Abstract: A processor including a pointer storage that stores pointer descriptors each including addressing information, an arithmetic logic unit (ALU) configured to execute an instruction which includes operand indexes each identifying a corresponding pointer descriptor, multiple address generation units (AGUs), each configured to translate addressing information from a corresponding pointer descriptors into memory addresses for accessing corresponding operands stored in a memory, and a smart cache. The smart cache includes a cache storage, and uses the memory addresses from the AGUs to retrieve and store operands from the memory into the cache storage, and to provide the stored operands to the ALU when executing the instruction. The smart cache replaces a register file used by a conventional processor for retrieving and storing operand information. The pointer operands include post-update capability that reduces instruction fetches. Wasted memory cycles associated with cache speculation are avoided.