Abstract: An apparatus for identifying active access, by a viewer, of a source containing an advertisement includes a video capture device for recording user interaction in an area and a video processor electrically coupled to the video capture device. The video processor is configured to analyze the video obtained by the video capture device. The video process analysis includes identification of active access, by the viewer, of the source containing the advertisement. The source is electrically decoupled from the video capture device.

Abstract: A method for sequential data storage. In an embodiment of such a method, a non-circular data structure is used for sequential data storage. The method includes dividing the non-circular data structure into a plurality of segments, where each segment includes a plurality of entries. The method further includes dynamically allocating the plurality of segments and sequentially associating the dynamically allocated segments.

Abstract: An apparatus for identifying active access, by a viewer, of a source containing an advertisement includes a video capture device for recording user interaction in an area and a video processor electrically coupled to the video capture device. The video processor is configured to analyze the video obtained by the video capture device. The video process analysis includes identification of active access, by the viewer, of the source containing the advertisement. The source is electrically decoupled from the video capture device.

Abstract: An apparatus for identifying active access, by a viewer, of a source containing an advertisement includes a video capture device for recording user interaction in an area and a video processor electrically coupled to the video capture device. The video processor is configured to analyze the video obtained by the video capture device. The video process analysis includes identification of active access, by the viewer, of the source containing the advertisement. The source is electrically decoupled from the video capture device.

Abstract: An apparatus for identifying active access, by a viewer, of a source containing an advertisement includes a video capture device for recording user interaction in an area and a video processor electrically coupled to the video capture device. The video processor is configured to analyze the video obtained by the video capture device. The video process analysis includes identification of active access, by the viewer, of the source containing the advertisement. The source is electrically decoupled from the video capture device.

Abstract: A hierarchical register file included in a hierarchical microprocessor that includes a plurality of execution clusters. An embodiment of the a hierarchical register file includes a first-level register file including a plurality of mappable registers. where the first level register filed is configured to allocate the mappable registers to store execution results of instructions executed by the execution clusters and provide secondary register storage for each of the execution clusters. The hierarchical register file also includes a plurality of second-level register files operatively coupled with the first-level register file, where the plurality of second-level register files are configured to store instruction operands and provide the instruction operands to respective execution units of the execution clusters for use in executing associated instructions.

Abstract: A hierarchical instruction scheduler included in a hierarchical microprocessor comprising a plurality of execution clusters. In one embodiment, a hierarchical instruction scheduler comprises a first-level instruction scheduler configured to receive instructions for execution; store first operand status information for respective operands of the instructions; and dispatch the instructions to respective execution clusters based on the instructions' respective first operand status information.

Abstract: A hierarchical store buffer included in a hierarchical microprocessor includes a plurality of execution clusters. An embodiment of a hierarchical store buffer includes a first-level store buffer configured to receive data values to be written to a memory subsystem from the plurality of execution clusters and store the received data values prior to writing the data values to the memory subsystem and a plurality of second-level store buffers each operatively coupled with the first-level store buffer, each second-level store buffer being included in a respective execution cluster.

Abstract: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.

Abstract: A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element, and one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements, where the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements and the plurality of execution clusters.

Abstract: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems. In an example embodiment, a processor includes a plurality of branch predictors. Each branch predictor is adapted to provide a prediction and an override signal. In the example embodiment, the processor futher includs a branch prediction control circuit. The branch prediction circuit is adapted to generate a branch prediction based on the prediction and the override signal from each predictor.

Abstract: A hierarchical store buffer included in a hierarchical microprocessor includes a plurality of execution clusters. An embodiment of a hierarchical store buffer includes a first-level store buffer configured to receive data values to be written to a memory subsystem from the plurality of execution clusters and store the received data values prior to writing the data values to the memory subsystem and a plurality of second-level store buffers each operatively coupled with the first-level store buffer, each second-level store buffer being included in a respective execution cluster.

Abstract: A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element, and one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements, where the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements and the plurality of execution clusters.

Abstract: A hierarchical register file included in a hierarchical microprocessor that includes a plurality of execution clusters. An embodiment of the a hierarchical register file includes a first-level register file including a plurality of mappable registers. where the first level register filed is configured to allocate the mappable registers to store execution results of instructions executed by the execution clusters and provide secondary register storage for each of the execution clusters. The hierarchical register file also includes a plurality of second-level register files operatively coupled with the first-level register file, where the plurality of second-level register files are configured to store instruction operands and provide the instruction operands to respective execution units of the execution clusters for use in executing associated instructions.

Abstract: A hierarchical instruction scheduler included in a hierarchical microprocessor comprising a plurality of execution clusters. In one embodiment, a hierarchical instruction scheduler comprises a first-level instruction scheduler configured to receive instructions for execution; store first operand status information for respective operands of the instructions; and dispatch the instructions to respective execution clusters based on the instructions' respective first operand status information.

Abstract: A method for sequential data storage. In an embodiment of such a method, a non-circular data structure is used for sequential data storage. The method includes dividing the non-circular data structure into a plurality of segments, where each segment includes a plurality of entries. The method further includes dynamically allocating the plurality of segments and sequentially associating the dynamically allocated segments.