Abstract: The present invention provides a method and apparatus for the efficient implementation of a totally general convolutional interleaver in a discrete multi-tone (DMT)-based digital subscriber line (xDSL) system, such as a modem or the like, that uses forward error correction (FEC) and convolutional interleaving to combat the effects of impulse noise and the like. More specifically, the present invention provides a method and apparatus for implementing a general convolutional interleaver, with no constraints, in an efficient manner, using (D?1)*(I?1)/2 memory locations for the interleaved data in all cases.

Abstract: The present invention provides procedures for computing Forward Error Correction (FEC) parameters given a set of constraints on maximum interleaver memory, maximum interleaver depth, maximum codeword size, maximum number of check bytes, maximum number of FEC codewords per Discrete Multi-Tone (DMT) symbol, and minimum number of DMT symbols that the FEC must correct, as well as any constraints imposed by the interleaver. These procedures are implemented on a computational engine in a modem, enabling it to achieve optimal performance in all cases. In addition these procedures can be applied as part of any bit loading algorithm to determine the optimal FEC parameters, taking into account the Signal-to-Noise Ratio (SNR) profile, the FEC coding gain, the constraints of the framer, and any application specific constraints.

Abstract: A digital receive filter comprises first and second filter parts with a down sampler between them. Each filter part is formed by a plurality of cascaded filter stages each comprising a second order finite impulse response digital filter having symmetrical coefficients which in most cases are integer powers of two, and in other cases are zero or a sum of integer powers of two. The filter stages are implemented by delay units and add units with shifting of bits at the inputs of the add units to implement the coefficients, whereby multipliers are avoided. A described receive filter has two filter stages in the first part, a down sampling factor of two, and seven filter stages in the second part, with scaling factors and ordering of the filter stages to facilitate filtering and minimize noise.

Abstract: In order to deal with echoes having exceptionally long tails, such as are generated by 2B1Q signals in ISDN systems, an echo canceller comprises a first echo cancelling means, conveniently a transversal filter, operative over a first number of baud periods, and filter means, conveniently an infinite impulse response filter, operative over a later number of baud periods. The filter means responds to each symbol of the transmitted signal to generate a pulse response which decays exponentially according to a predetermined function. The echo canceller further comprises means for subtracting the outputs of the first echo cancelling means and the filter means, respectively, from the received signal. The filter means may have more than one tap, enabling the exponential decay function to be adjusted to give a closer approximation to the shape of the echo tail.

Abstract: A digital signal processor which efficiently executes the division of a positive number in N+1 processor cycles where N is equal to the number of digits in the dividend. This is achieved by utlizing an arithmetic logic unit in the processor which is divided into two selectively concatenated independently controllable sections so that the values therein can be selectively processed under control of a unique algorithm.