Abstract: A liquid crystal display includes pixels that are arranged in columns and rows. Data line drivers responsive to a video signal develop output signals in data lines that correspond with the columns, respectively. An adjustment data line driver is provided. The adjustment data line driver is responsive to a reference DC constant signal at a mid-range of the video signal. An output signal of the adjustment data line driver is coupled to the other data line drivers in a negative feedback manner to compensate for output signal variations in the other data line drivers.

Abstract: A level translator includes a latch, a pair of transistors responsive to a switching input voltage and operating in a complementary manner and a pair of zener diodes operating as level shifters. The Zener diodes are coupled between the pair of transistors and the latch. An output transistor is coupled to the latch and produces an output voltage that is level translated with respect to the input voltage. A second embodiment of the invention includes a level translator that produces a first voltage at selectively one of first and second levels and a second voltage at selectively one of third and fourth levels. The first, second, third and fourth levels are different from each other such that in total four different levels are produced. The first and second voltages are coupled to control gates of a pair of transistors operating as a transmission gate.

Abstract: There is described an electronic interrogation and identification (I/I) system in which an interrogator/reader (I/R) unit operates remotely using a microwave beam in conjunction with one or more coded articles. The articles are identified by a unique method and search sequence. As the I/R unit interrogates the articles, one or more of them respond to the I/R unit whenever a code word (data value) sent from the I/R unit matches a code word stored in one or more of the memory positions within the articles. After searching through all of the possible code words and word positions the I/R unit will have identified at least one code word stored in each of the word positions of at least one article. Then combinations of the just-identified code words are matched with the respective stored words of the various articles. After being uniquely identified each article is "powered-down" on command from the I/R unit and remains inactive so that one-by-one all remaining articles are also identified.

Abstract: There is described an electronic interrogation and identification (I/I) system in which an interrogator/reader (I/R) unit operates remotely using a microwave beam in conjunction with one or more coded articles. The articles are identified by a unique method and search sequence. As the I/R unit interrogates the articles, one or more of them respond to the I/R unit whenever a code word (data value) sent from the I/R unit matches a code word stored in one or more of the memory positions within the articles. After searching through all of the possible code words and word positions the I/R unit will have identified at least one code word stored in each of the word positions of at least one article. Then combinations of the just-identified code words are matched with the respective stored words of the various articles. After being uniquely identified each article is "powered-down" on command from the I/R unit and remains inactive so that one-by-one all remaining articles are also identified.

Abstract: A differential comparator includes first and second transistors for comparing an input signal to a reference signal during a comparison phase and circuitry for balancing the quiescent currents through the transistors. The circuitry includes a first current source connected to the source of the first transistor, a second current source connected to the source of the second transistor and a selectively enabled impedance means connected between the sources of the two transistors. Prior to each comparison phase the currents through the first and second transistors are balanced (i.e. made approximately equal) by application of equal voltages to the gates of the two transistors and cross-coupling the source potentials of the first and second transistors to control the second and first current sources.

Abstract: A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node.

Abstract: A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks.

Abstract: A precise, high speed CMOS track (sample)/hold circuit uses a first circuit leg including four Schottky barrier diodes configured to form a Wheatstone bridge, a second leg with a single n-channel MOS transistor, an essentially constant current source having MOS transistors, a capacitor for holding output signal, and reverse biasing circuitry having MOS transistors for selectively reverse biasing the four diodes. An analog input signal is applied to the cathode of the first diode and to the anode of the second diode. An output signal of the same magnitude and polarity as the input signal is generated at an output terminal (the cathode of the third diode and the anode of the fourth diode) of the circuit when current flows through the first circuit leg.

Abstract: There is disclosed a decoder configuration for a high-speed flash-type analog-to-digital converter which utilizes a plurality of comparators arranged from a first lower order comparator to a last high order comparator based on the particular position of each comparator as coupled to taps of a reference resistance ladder. The measurement point in such a system can be logically decoded by establishing the tap where all comparators below it are low and ideally all comparators above the tap are high. This is implemented in a decoding scheme which implements the test by testing all combinations of three adjacent comparators so that the selected tap is high and the taps immediately above and below it are high and low respectively to therefore detect an HHL sequence. In regard to the present invention, there are included means which will prevent a higher order HHL sequence from appearing when a lower order HHL sequence is detected.

Abstract: A twelve bit analog-to-digital converter uses two banks of 31 capacitors each coupled through separate control circuitry to a five bit analog-to-digital converter with plus or minus 1/2 bit accuracy and two separate eight bit analog-to-digital converters each having plus or minus 1/2 bit accuracy to achieve a frequency of operation from at least several MHz to up to about 40 MHz.

Abstract: A transmission gate employs a pair of capacitors ahead of and a pair of capacitors behind a transistor. One capacitor of each pair is supplied with a control voltage pulse that leads and the other with a control voltage pulse that lags the complement of a control voltage pulse supplied to the gate of the transistor. The capacitors are typically each a MOS transistor with the gate serving as one terminal and the drain and source shorted together and serving as the other terminal. Moreover, each of the capacitors has a capacitance equal to one half the capacitance of the gate to source and gate to drain capacitance of the transistor. This circuitry makes possible charge compensation to avoid the build up of trapped charge in the transistor.

Abstract: A near unity gain, essentially zero-offset, high input impedance, relatively low output impedance, fast responding buffer circuit uses first and second essentially identical n-channel depletion mode MOS transistors with the drain-source circuitries serially connected together and with the gate and source of the second transistor connected together. A first feedback circuit, which uses a first n-channel enhancement mode MOS transistor as a voltage level shifter and a third n-channel depletion mode MOS transistor as a source follower, is connected between the source and drain of the first transistor. A second feedback circuit, which uses a second n-channel enhancement mode MOS transistor as a voltage level shifter and a fourth n-channel depletion mode MOS transistor as a source follower, is connected between the source and drain of the second transistor. The gate and source of the first transistor serve as the buffer input and output terminals, respectively.

Abstract: Integral linearity error in the operating characteristics of an analog to digital converter employing sampling comparators is reduced by recurrently connecting at least one resistive shunt across a predetermined central portion of a reference voltage divider input to the comparators. The shunt resistance is approximately an order of magnitude larger than the resistance of the shunted part of the divider. Each recurrent connection interval is of fixed duration independent of sampling rate, and each interval spans the beginning of a recurrent time of connection of said divider to said comparators.

Abstract: A digital to analog converter including an R-2R ladder network receives digitally encoded sample signals in parallel through a set of chains of transistor switches, each chain having equal delay. The ladder network output impedance matches the characteristic impedance of a coaxial cable transmission line that couples the converter output to a utilization circuit. Output resistances of the switches which are connected to ladder network rung circuits are scaled in accordance with a predetermined algorithm to maintain symmetry of parallel connected resistive branches of the latter network seen at each rail terminal of the ladder. Three of the most significant bits of each input binary coded work are decoded to a bar code format before being coupled through the set of switch chains.

Abstract: An impedance transforming circuit for multibit digital word signals includes plural transmission paths for respective signals of a word. At least some of the paths have different output impedances but present essentially the same signal propagation delay. Each path includes plural, tandem connected, transistor switches; and each switch comprises, with correspondingly located switches of other paths, a stage of the transforming circuit. Output conductances of the switches of a path are scaled along the path according to a stage-to-stage ration F selected to minimize the number of stages required to achieve a desired signal propagation time through the path. At any stage switch where the ratio F cannot be directly accommodated, the selected value of F is achieved by dividing the stage output conductance between an in-path switch, that satisfies that ratio F with respect to a driven stage and a dummy-load switch that, together with the in-path switch, satisfies the ratio F with respect to a prior stage switch.

Abstract: A subranging analog-to-digital converter is disclosed. A coarse analog-to-digital converter has an analog input terminal coupled to a source of analog signal, a digital output terminal, and a range indication output terminal. First and second fine analog-to-digital converters each have an analog input terminal coupled to the analog signal source, a range selection input terminal coupled to the range indication output terminal, and a digital output terminal. A combining circuit has input terminals coupled to the digital output terminals of the coarse and first and second fine analog-to-digital converters. The coarse analog-to-digital converter operates on every clock cycle, and the fine analog-to-digital converters operate alternately on every other clock cycle to produce a sequence of digital samples representing the analog signal, one for each clock cycle.

Abstract: The memory cell is a five transistor cell formed with complementary symmetry metal oxide (CMOS) semiconductor insulated gate field effect transistors (IGFETs) in the silicon-on-sapphire (SOS) technology with doped polycrystalline interconnects using buried contacts. Diodes are formed where doped polycrystalline silicon lines form buried contacts to underlying silicon epitaxial regions of opposite conductivity type and where silicon epitaxial regions of opposite conductivity type contact one another. The presence of these diodes has been shown by the inventor to not be detrimental to the operation of the memory cell.

Abstract: In a comparator circuit, first and second latchable circuits are connected in cascade between the output of an amplifying stage and the input of a decoder to enable the comparator to operate at significantly higher frequencies with lower error levels. An input signal, to be sampled, and a reference signal are applied to the input of the amplifying stage and a "sampled" signal indicative of the difference between the input and the reference is produced at the output of the amplifying stage. The "sampled" signal produced at the output of the amplifying stage is first processed, via the first latchable circuit operated in a regenerative mode to enhance the signal, during one time interval. The enhanced signal is then processed via the second latchable circuit operated in a regenerative mode tending to further enhance the signal, during a second, succeeding, time interval, for application to the decoder.

Abstract: Clock shaping means responsive to the frequency of an incoming clock signal (CL.sub.I) produce asymmetrical clocking signals whose high to low ratio varies as a function of the frequency of CL.sub.I. The asymmetrical clocking signals when applied to A/D converters, improve their performance and extend their operating range as a function of frequency.

Abstract: In an A/D converter, a resistive network for producing 2.sup.n different voltage steps. The resistive network includes a coarse relatively high impedance resistive string which is subdivided into 2.sup.x coarse segments. The resistive network also includes a fine relatively high impedance resistive network comprised of a fine resistive element per coarse segment. Each fine resistive element is then subdivided into 2.sup.(n-x) fine sub-segments. In determining the value of an input voltage being sensed, all the coarse segments are used to sense which coarse segments brackets the input voltage. However, only the fine segment in parallel with the "bracketing" coarse resistor is then coupled to comparator means to sense which fine sub-segment brackets the input voltage.