Patents by Inventor Andrew G. Norman

Andrew G. Norman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8961687
    Abstract: Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InxGayAl1-x-yN alloy. The lattice parameter of the InxGayAl1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a?)=?2(a) or (a?)=(a)/?2. The semiconductor alloy may be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 24, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Patent number: 8575471
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 5, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Patent number: 8507365
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a?) that is related to the substrate lattice parameter (a). The lattice parameter (a?) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 13, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak
  • Publication number: 20110147791
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a?) that is related to the substrate lattice parameter (a). The lattice parameter (a?) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak
  • Publication number: 20110049520
    Abstract: Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InxGayAl1-x-yN alloy. The lattice parameter of the InxGayAl1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a?)=?2(a) or (a?)=(a)/?2. The semiconductor alloy may be prepared to have a selected band gap.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: Andrew G. Norman, Aaron Ptak, William E. McMahon
  • Publication number: 20110048514
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a metal or metal alloy substrate having a crystalline surface with a known lattice parameter (a). The methods further include growing a crystalline semiconductor alloy layer on the crystalline substrate surface by coincident site lattice matched epitaxy. The semiconductor layer may be grown without any buffer layer between the alloy and the crystalline surface of the substrate. The semiconductor alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter (a). The semiconductor alloy may further be prepared to have a selected band gap.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLC
    Inventors: ANDREW G. NORMAN, Aaron Ptak, William E. McMahon
  • Patent number: 7229498
    Abstract: Nanostructures (18) and methods for production thereof by phase separation during metal organic vapor-phase epitaxy (MOVPE). An embodiment of one of the methods may comprise providing a growth surface in a reaction chamber and introducing a first mixture of precursor materials into the reaction chamber to form a buffer layer (12) thereon. A second mixture of precursor materials may be provided into the reaction chamber to form an active region (14) on the buffer layer (12), wherein the nanostructure (18) is embedded in a matrix (16) in the active region (14). Additional steps are also disclosed for preparing the nanostructure (18) product for various applications.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: June 12, 2007
    Assignee: Midwest Research Institute
    Inventors: Andrew G. Norman, Jerry M. Olson