Patents by Inventor Andrew Gaul
Andrew Gaul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145584Abstract: A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Inventors: Julien Frougier, Kangguo Cheng, Ruilong Xie, Chanro Park, Andrew Gaul, Min Gyu Sung
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Patent number: 11935930Abstract: Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.Type: GrantFiled: November 30, 2021Date of Patent: March 19, 2024Assignee: International Business Machines CorporationInventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park, Andrew Gaul
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Publication number: 20240072041Abstract: Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: Andrew Gaul, Anthony I. Chou, Julien Frougier, Andrew M. Greene
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Patent number: 11742350Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.Type: GrantFiled: September 23, 2021Date of Patent: August 29, 2023Assignee: International Business Machines CorporationInventors: Andrew Gaul, Chanro Park, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
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Publication number: 20230178587Abstract: An approach provides a metal-insulator-metal capacitor with a comb-like structure. The metal-insulator-metal capacitor includes a first electrode material forming a central, vertical portion of the first electrode metal and two sets of stacked horizontal portions of the first electrode metal. An insulator material surrounds the first electrode metal and exposes a top surface of the central, vertical portion of the first electrode metal. The metal-insulator-metal capacitor includes a second electrode material surrounding the insulator material. The metal-insulator-metal capacitor includes a first electrode contact connecting to the top surface of the central, vertical portion of the first electrode metal and a second electrode contact connecting to a top surface of the second electrode material.Type: ApplicationFiled: December 5, 2021Publication date: June 8, 2023Inventors: Julien Frougier, Ruilong Xie, Veeraraghavan S. Basker, Andrew Gaul
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Publication number: 20230170394Abstract: Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Julien FROUGIER, Ruilong XIE, Kangguo CHENG, Chanro PARK, Andrew GAUL
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Publication number: 20230170396Abstract: Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park, Andrew Gaul
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Publication number: 20230143317Abstract: A semiconductor device includes a first gate upon a semiconductor substrate and a second gate upon the semiconductor substrate in line with the first gate. A gate cut dielectric is between the first gate and the second gate. A first gate cap is upon a top surface of the first gate and a second gate cap is upon a top surface of the second gate. A gate cut multilayer structure is between the first gate cap and the second gate cap. The gate cut multilayer structure includes a dielectric between a first substantially vertical spacer and a second substantially vertical spacer. A first sidewall of the multilayer structure is coplanar with an end of the first gate and a second opposing sidewall of the multilayer structure is coplanar with an end of the second gate.Type: ApplicationFiled: November 11, 2021Publication date: May 11, 2023Inventors: CHANRO PARK, Andrew M. Greene, Andrew Gaul, Ruilong Xie
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Patent number: 11646306Abstract: An apparatus that includes a substrate divided into a plurality of different regions, where the substrate remains physically together. A first device located in a first region of the plurality of different regions, where the first device has a first height. A second device located in a second region of the plurality of different regions. The second device has a second height and the second device is a different device from the first device. A third device located in a third region of the plurality of different regions. The third device has a third height and the third device is a different device from the first device and the second device. The second height is smaller than the first height.Type: GrantFiled: March 24, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Julien Frougier, Veeraraghavan S. Basker, Andrew Gaul, Ruilong Xie
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Publication number: 20230105783Abstract: Semiconductor structures are disclosed which comprise semiconductor devices having thin multi-layer channel stacks. In one example, a semiconductor structure comprises a gate structure comprising a multi-layer channel stack. The multi-layer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further comprises a first source/drain region disposed on a first side of the gate structure and in electrical contact with a first end portion of the multi-layer channel stack and a second source/drain region disposed on a second side of the gate structure and in electrical contact with a second end portion of the multi-layer channel stack.Type: ApplicationFiled: September 27, 2021Publication date: April 6, 2023Inventors: ANDREW GAUL, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz, Kangguo Cheng
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Publication number: 20230093343Abstract: A stacked device is provided. The stacked device includes a plurality of dielectric support bridges on a substrate, and a first two-dimensional (2D) channel layer on each of the plurality of dielectric support bridges. The stacked device further includes a gate dielectric sheet on the first two-dimensional (2D) channel layer, and a second two-dimensional (2D) channel layer on the first two-dimensional (2D) channel layer. The stacked device further includes a second gate dielectric layer on the gate dielectric sheets.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Andrew Gaul, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
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Publication number: 20230086785Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Andrew Gaul, CHANRO PARK, Julien Frougier, Ruilong Xie, Andrew M. Greene, Christopher J. Waskiewicz
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Publication number: 20220310590Abstract: An apparatus comprising a substrate divided into a plurality of different regions, wherein the substrate remains physically together. A first device located in a first region of the plurality of different regions, wherein the first device has a first height. A second device located in a second region of the plurality of different regions, wherein the second device has a second height, wherein the second device is a different device from the first device. A third device located in a third region of the plurality of different regions, wherein the third device has a third height, wherein the third device is a different device from the first device and the second device. Wherein the second height is smaller than the first height.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Inventors: Julien Frougier, Veeraraghavan S. Basker, Andrew Gaul, Ruilong Xie
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Patent number: 11016933Abstract: Techniques to manage the use of hash functions are disclosed. In various embodiments, a hash function epoch metadata is stored to associate a hash function with an epoch, the epoch defining a subset of data stored by a distributed file system. The distributed file system is configured to use the hash function epoch metadata to manage storage of data comprising the subset of data stored by the distributed file system.Type: GrantFiled: February 7, 2019Date of Patent: May 25, 2021Assignee: EMC IP Holding Company LLCInventors: Mahadev Satyanarayanan, Niraj Tolia, Andrew Gaul
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Publication number: 20190188183Abstract: Techniques to manage the use of hash functions are disclosed. In various embodiments, a hash function epoch metadata is stored to associate a hash function with an epoch, the epoch defining a subset of data stored by a distributed file system. The distributed file system is configured to use the hash function epoch metadata to manage storage of data comprising the subset of data stored by the distributed file system.Type: ApplicationFiled: February 7, 2019Publication date: June 20, 2019Inventors: Mahadev Satyanarayanan, Niraj Tolia, Andrew Gaul
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Patent number: 10242015Abstract: Techniques to manage the use of hash functions are disclosed. In various embodiments, a hash function epoch metadata is stored to associate a hash function with an epoch, the epoch defining a subset of data stored by a distributed file system. The distributed file system is configured to use the hash function epoch metadata to manage storage of data comprising the subset of data stored by the distributed file system.Type: GrantFiled: August 18, 2015Date of Patent: March 26, 2019Assignee: EMC IP Holding Company LLCInventors: Mahadev Satyanarayanan, Niraj Tolia, Andrew Gaul
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Patent number: 9178860Abstract: A method in data storage involves receiving at a metadata server from a client device a BEGIN_WRITE request identifying data to be written by hashes, consulting, by the metadata server a deduplication table to determine historical nature of the data determined to be written, determining that the data was never previously written, was previously written by another client, or was previously written but failed a verification, sending to the client device write locations with tokens for the data, starting an authentication timer, and authorizing the client device to write directly to the data server using the authentication tokens and the authenticated write locations, determining that the data was previously written by the same client, or that the data was previously written and passed the verification test, notifying the client of this circumstance, and receiving from the client device an END_WRITE request.Type: GrantFiled: August 22, 2013Date of Patent: November 3, 2015Assignee: Maginatics, Inc.Inventors: Niraj Tolia, Diwaker Gupta, Andrew Gaul
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Publication number: 20150058935Abstract: A method in data storage involves receiving at a metadata server from a client device a BEGIN_WRITE request identifying data to be written by hashes, consulting, by the metadata server a deduplication table to determine historical nature of the data determined to be written, determining that the data was never previously written, was previously written by another client, or was previously written but failed a verification, sending to the client device write locations with tokens for the data, starting an authentication timer, and authorizing the client device to write directly to the data server using the authentication tokens and the authenticated write locations, determining that the data was previously written by the same client, or that the data was previously written and passed the verification test, notifying the client of this circumstance, and receiving from the client device an END_WRITE request.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Applicant: Maginatics, Inc.Inventors: Niraj Tolia, Diwaker Gupta, Andrew Gaul