Patents by Inventor Andrew Gerard Noonan

Andrew Gerard Noonan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Printed circuit board connection for integrated circuits using two routing layers
    Patent number: 10709019
    Abstract: Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 7, 2020
    Assignee: Google LLC
    Inventors: Andrew Gerard Noonan, Sara Zebian
  • Printed circuit board connection for integrated circuits using two routing layers
    Patent number: 10617009
    Abstract: Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 7, 2020
    Assignee: Google LLC
    Inventors: Andrew Gerard Noonan, Sara Zebian