Patents by Inventor Andrew Glew

Andrew Glew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080052500
    Abstract: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 28, 2008
    Applicant: Centaurus Data LLC
    Inventor: Andrew Glew
  • Patent number: 7318141
    Abstract: Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventors: Steve M. Bennett, Gilbert Neiger, Erik C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Richard A. Uhlig, Larry Smith, Dion Rodgers, Andrew Glew, Erich Boleyn
  • Publication number: 20070083735
    Abstract: Various embodiments are described relating to hierarchical processors.
    Type: Application
    Filed: August 29, 2005
    Publication date: April 12, 2007
    Inventor: Andrew Glew
  • Publication number: 20070083739
    Abstract: Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.
    Type: Application
    Filed: August 29, 2005
    Publication date: April 12, 2007
    Inventor: Andrew Glew
  • Publication number: 20050038977
    Abstract: A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.
    Type: Application
    Filed: September 13, 2004
    Publication date: February 17, 2005
    Inventors: Andrew Glew, Larry Mennemeier, Alexander Peleg, David Bistry, Millind Mittal, Carole Dulong, Eiichi Kowashi, Benny Eitan, Derrick Lin, Ramamohan Vakkalagadda
  • Publication number: 20040117539
    Abstract: Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Applicant: Intel Corporation
    Inventors: Steve M. Bennett, Gilbert Neiger, Erik C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Richard A. Uhlig, Larry Smith, Dion Rodgers, Andrew Glew, Erich Boleyn
  • Patent number: 5948097
    Abstract: A method and apparatus for performing a system call in a system having a user privilege level and a kernel privilege level, wherein the kernel privilege level is higher than the user privilege level is disclosed. A sequence of instructions is executed at the user privilege level including a first instruction that requires a resource provided at the kernel privilege level. Control is transferred to a first procedure executing at the user privilege level by performing a near call and saving only a pointer to the first instruction. The first procedure includes a calling instruction that does not save an architectural state prior to transferring control. Control is transferred from the first procedure to a second procedure executing at the kernel privilege level. The second procedure determines the resource required by the first instruction. Control is transferred from the second procedure to a third procedure that is determined by the second procedure.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: September 7, 1999
    Assignee: Intel Corporation
    Inventors: Andrew Glew, Scott Dion Rodgers
  • Patent number: 5724527
    Abstract: A multiprocessor computing system includes a serial bus and implements a boot protocol in which each processor compares a vector field of a boot message issued on the serial bus by a first processor with an ID of the processor; a match indicating that the first processor is a bootstrap processor (BSP). The non-BSPs are halted and, after issuing a final message on the bus, the BSP fetches code to start a reset sequence. The BSP then sends a message to wake the non-BSPs, after which time the operating system software is given control. Faulty processors that fail to participate in the boot protocol do not stop the selection of a BSP as long as one processor in the system is functional.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: March 3, 1998
    Assignee: Intel Corporation
    Inventors: Milind Karnik, Joseph Batz, Keshavan Tiruvallur, Andrew Glew, Frank Binns, Shreekant Thakkar, Nitin Sarangdhar