Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of storing an object within a managed object space of the nonvolatile memory includes the step of determining an object class for the object. Objects of a first class are stored contiguously proceeding from a first end towards a second end of the managed object space to form a first class of space. Objects of a second class are stored contiguously proceeding from the second end towards the first end of managed object space to form a second class of space. A header identifying the object is stored at a bottom of the first class of space. The object is stored at a selected one of the bottom of the first class of space and a bottom of the second class of space in accordance with the object class.

Abstract: An arrangement for accessing a non-volatile memory array including providing a signal having a first condition if an access is a read and a second condition if an access is for any other operation; reading data directly from an address in the non-volatile memory array if the signal is a first condition; and performing any other access of the non-volatile memory array utilizing a command-centric interface if the signal is a second condition.

Abstract: A method and apparatus for interfacing a data bus to a plurality of memory devices. A portion of data associated with a first address is loaded into a first cell in a first memory device. Another portion of data associated with the first address is loaded into a second cell in a second memory device. Subsequently, a portion of data associated with a second address is loaded into a third cell in the first memory device while another portion of data associated with the second address is loaded into a fourth cell in a third memory device.

Abstract: A system for enabling a PC card to appropriately function in the 16-bit and 32-bit standard PCMCIA environments. If the 16-bit standard and the 32-bit standard requires a pin to be connected in a certain manner, then the pin is connected in that manner. If the 16-bit standard requires a card detect pin to be grounded and the 32-bit standard requires that same card detect pin to be connected to a voltage sense pin, then the card detect pin and voltage sense pin are connected, and the card detect pin is connected to ground via a pull-down resistor. After initialization, the standard of the PCMCIA adapter can be detected by sensing the voltage of an open-circuited voltage sense pin.