Patents by Inventor Andrew Ha

Andrew Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200097916
    Abstract: A system is provided for providing automated early dispersals of accrued but unpaid wages to a worker who has accrued wages from one or more employers. The system includes one or more customizable applications associated with the system, a communications platform in the form of an application programming interface for integrating and communicating in real-time with one or more databases containing employment and accrued wages information, a processor and memory that stores instructions from each of the one or more customizable applications.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Tate Hunter Hackert, Darcy Allan Tuer, Jamie Nghi Ha, Garth Andrew McAdam
  • Patent number: 10578097
    Abstract: A method for pumping a fluid includes providing a peristaltic pump including a contact wall, an opposing, movable compression element, and a flexible tube interposed between the contact wall and the compression element in a compressing region. The flexible tube has a tube lengthwise axis and a through passage. The flexible tube is displaceable relative to the compressing region between a first position and a second position different from the first position. The method includes: with the flexible tube in the first position, compressing the flexible tube between the compression element and the contact wall to thereby force the fluid through the through passage; thereafter displacing the flexible tube into the second position from the first position; and thereafter, with the flexible tube in the second position, compressing the flexible tube between the compression element and the contact wall to thereby force the fluid through the through passage.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 3, 2020
    Assignee: PerkinElmer Health Sciences, Inc.
    Inventors: Tak Shun Cheung, Chui Ha Cindy Wong, Andrew Icasiano
  • Patent number: 10468660
    Abstract: A secondary battery includes: an electrode assembly; a case accommodating the electrode assembly; an electrode tab extending from the electrode assembly; a sealing part for insulating the electrode tab from the case; and an insulation film around the electrode tab and between the sealing part and the electrode assembly.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 5, 2019
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Taegon Kim, Andrew Kim, Youngkwang Yun, Joonsup Kim, Jaehyung Kim, Hoseong Kim, Kichul Ham, Minhee Lee, Daesung Ro, Jaehee Ha, Junhyung Lee, Jungmin Kang, Junggun Lim, Jaehee Kyoung, Jinwoo Kim
  • Publication number: 20190258775
    Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 22, 2019
    Inventors: MOON-SU KIM, Naya Ha, Jong-ku Kang, Andrew Paul Hoover
  • Patent number: 10372869
    Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon-Su Kim, Naya Ha, Jong-Ku Kang, Andrew Paul Hoover
  • Patent number: 10332748
    Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: June 25, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
  • Publication number: 20190172031
    Abstract: A method to facilitate invoicing for transactions established utilizing a network-based transaction system includes supporting establishment of transactions between a plurality of entities in the network-based transaction system, and identifying as part of an invoice generation process, a plurality of transactions to which a first entity is a party. The method further includes identifying first and second transactions from the plurality of transactions that satisfy combinable criteria, and generating an invoice for at least the first and second transactions that satisfy the combinable criteria. The method can also be implemented in a system and on a machine-readable medium.
    Type: Application
    Filed: October 23, 2018
    Publication date: June 6, 2019
    Inventors: Paul Fu, Erik Hansen, George Liang, Deborah Liu, Ngan-Ha D. Nguyen, Andrew Leigh Sandler
  • Publication number: 20180326558
    Abstract: A vise includes a base and two opposed jaws. At least one of the jaws is movable with respect to the other so that an object can be gripped therebetween. At least one of the two opposed jaws includes a frame and an array of polygon-shaped pins stacked parallel to one another. The frame has a bottom side and two opposed sides tapering towards the bottom side. The pins are disposed on the bottom side. Each pin has a cross-sectional shape such that when stacked together, the pins fit flush with one another and an area defined by the frame is tiled by the pins without any substantial gaps therebetween. The pins are oriented such that the tapering opposed sides direct force vectors to increase a pin-to-pin clamping force and the frame selectively clamps down on the pins such that the pins are held in place.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 15, 2018
    Inventors: Mark Andrew Atwater, Andrew Ha
  • Patent number: 6490638
    Abstract: A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose peripherals connected to the bus and enables external devices to be connected with proper timing to the microcontroller. The general purpose bus controller includes programmable interface timing control logic which allows the bus cycle length for commands from a processor or other bus master to be programmed. Accordingly, memory and I/O read and write commands are customized to suit the timing requirements of peripheral devices connected externally to the microcontroller. A significant variety of peripheral devices may thus be coupled to the microcontroller without requiring additional glue logic. The general purpose bus controller further includes an echo mode which permits accesses to internal peripheral devices to be interpreted by a logic analyzer or other debugging equipment.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: December 3, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew Ha, Pratik M. Mehta