Abstract: A vise includes a base and two opposed jaws. At least one of the jaws is movable with respect to the other so that an object can be gripped therebetween. At least one of the two opposed jaws includes a frame and an array of polygon-shaped pins stacked parallel to one another. The frame has a bottom side and two opposed sides tapering towards the bottom side. The pins are disposed on the bottom side. Each pin has a cross-sectional shape such that when stacked together, the pins fit flush with one another and an area defined by the frame is tiled by the pins without any substantial gaps therebetween. The pins are oriented such that the tapering opposed sides direct force vectors to increase a pin-to-pin clamping force and the frame selectively clamps down on the pins such that the pins are held in place.

Abstract: A vise includes a base and two opposed jaws. At least one of the jaws is movable with respect to the other so that an object can be gripped therebetween. At least one of the two opposed jaws includes a frame and an array of polygon-shaped pins stacked parallel to one another. The frame has a bottom side and two opposed sides tapering towards the bottom side. The pins are disposed on the bottom side. Each pin has a cross-sectional shape such that when stacked together, the pins fit flush with one another and an area defined by the frame is tiled by the pins without any substantial gaps therebetween. The pins are oriented such that the tapering opposed sides direct force vectors to increase a pin-to-pin clamping force and the frame selectively clamps down on the pins such that the pins are held in place.

Abstract: A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose peripherals connected to the bus and enables external devices to be connected with proper timing to the microcontroller. The general purpose bus controller includes programmable interface timing control logic which allows the bus cycle length for commands from a processor or other bus master to be programmed. Accordingly, memory and I/O read and write commands are customized to suit the timing requirements of peripheral devices connected externally to the microcontroller. A significant variety of peripheral devices may thus be coupled to the microcontroller without requiring additional glue logic. The general purpose bus controller further includes an echo mode which permits accesses to internal peripheral devices to be interpreted by a logic analyzer or other debugging equipment.