Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

Abstract: Improved biopharmaceutical processing equipment such as reactor vessels and stainless steel surfaces, and methods of determining the same are disclosed herein. In some embodiments, a biopharmaceutical processing equipment can include a vessel having a surface that is configured to contact proteinaceous processing material, wherein the surface has a pre-commissioning surface roughness of greater than about 20 Ra Max (?in).

Abstract: Autotagging a template of a reporting workbook is provided. The template of the reporting workbook is received. The template is in a first format type. User specified selection of portions of the template are received. The portions are associated with at least two dimensions of the reporting workbook. A user specified type is received for a tag. A modification of the template is created by automatically generating a tag in a predetermined field of each of the portions based on the user specified type. A version of the reporting workbook is generated based on the modification of the template, wherein the version is in a second format type.

Abstract: Aspects include performing online condition monitoring. Online condition monitoring includes compiling the digital sensor data to produce compiled data and processing the compiled data via a signal analysis operation to produce digitally analyzed data. Further, online condition monitoring includes comparing the digitally analyzed data to at least one threshold to output corresponding values and utilizing the corresponding value to determine whether to issue an event notification.

Abstract: Disclosed is a computerized method, non-transitory machine-readable medium and computer system for ensuring that critical information, such as that allowing an ecommerce customer to activate purchased downloadable software, can be retrieved even if issues occur in the primary distribution center. The method receives a call for data (e.g. key) at a first endpoint associated with a first distribution center, determining that the call for the data cannot be fulfilled at the first endpoint, and shifting the call for the data to a second endpoint associated with a second distribution center. The computer system comprises a first and second distribution center system, including modules for: fulfilling a call for data, or key; determining if a call cannot be fulfilled, determining a plurality of error indications; and redirecting calls originally directed to one of a first computer or a second computer to the other of the first computer and the second computer.

Abstract: Disclosed is a computerized method, non-transitory machine-readable medium and computer system for ensuring that critical information, such as that allowing an ecommerce customer to activate purchased downloadable software, can be retrieved even if issues occur in the primary distribution center. The method receives a call for data (e.g. key) at a first endpoint associated with a first distribution center, determining that the call for the data cannot be fulfilled at the first endpoint, and shifting the call for the data to a second endpoint associated with a second distribution center. The computer system comprises a first and second distribution center system, including modules for: fulfilling a call for data, or key; determining if a call cannot be fulfilled, determining a plurality of error indications; and redirecting calls originally directed to one of a first computer or a second computer to the other of the first computer and the second computer.

Abstract: Disclosed is a computerized method, non-transitory machine-readable medium and computer system for ensuring that critical information, such as that allowing an ecommerce customer to activate purchased downloadable software, can be retrieved even if issues occur in the primary distribution center. The method receives a call for data (e.g. key) at a first endpoint associated with a first distribution center, determining that the call for the data cannot be fulfilled at the first endpoint, and shifting the call for the data to a second endpoint associated with a second distribution center. The computer system comprises a first and second distribution center system, including modules for: fulfilling a call for data, or key; determining if a call cannot be fulfilled, determining a plurality of error indications; and redirecting calls originally directed to one of a first computer or a second computer to the other of the first computer and the second computer.

Abstract: An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Abstract: Methods of fabricating and prescribing lenses suitable for color blindness and dyslexia correction are disclosed. The corrective lens may be formed of an optically transparent base material, which is tinted to a desired color for correction by immersion in a colorant dye. The color tinted lens is then tinted by a neutral tint dye to render the lens observable as a regular corrective lens. Prescription of such lenses may be based on a dynamically balanced, or haploscopic, fashion of prescription that comprises selecting a first visual filter from a set of sixteen filters and a second visual filter from the remaining set of fifteen filters, the first for the dominant eye and the second for non-dominant eye.

Abstract: The systems and methods taught herein provide a choreographed, crowd forum at an event, including offering to send a media display to a plurality of participants in a crowd attending the event. Each of the plurality of participants have (i) a close-visual proximity to other participants; and, (ii) it's own respective computing device with a graphical user interface, a processor, a database, and a choreography. Each respective computing device is operable to at least receive and display a choreographed portion of the crowd media display. The choreographed portions can be configured to be received and displayed by each respective computing device in a choreographed manner in the crowd coordinated with an activity at the event. In this manner, the plurality of participants have at least the experience of receiving and displaying a respective choreographed portion of the crowd media display at the event.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: Systems and methods for payment processing on devices are provided. Such systems and methods enable payment processing to be completed with a peripheral device (such as a magnetic card reader) and a point of sales system, without the need for extensive developer integration. The system receives a payment charge amount from a point of sales system. The system also detects (or dynamically populates) peripheral devices that are used to capture account information. The peripheral device is a supported device type with an associated library, which includes data for properly interfacing with the peripheral device. The system provides the captured account data, a merchant ID and the amount of the charge to a payment management system. The system likewise receives a response (approve or decline) from the payment management system.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: The systems and methods taught herein provide a choreographed, crowd forum at an event, including offering to send a media display to a plurality of participants in a crowd attending the event. Each of the plurality of participants have (i) a close-visual proximity to other participants; and, (ii) it's own respective computing device with a graphical user interface, a processor, a database, and a choreography. Each respective computing device is operable to at least receive and display a choreographed portion of the crowd media display. The choreographed portions can be configured to be received and displayed by each respective computing device in a choreographed manner in the crowd coordinated with an activity at the event. In this manner, the plurality of participants have at least the experience of receiving and displaying a respective choreographed portion of the crowd media display at the event.

Abstract: A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Abstract: A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

Abstract: A display arrangement comprises a banner, one edge of which is secured to a hollow, flexible rod. A spring arrangement is located within the rod. The spring arrangement comprises a spring that extends along a predetermined length of the rod and an elastic band that is looped through the length of the rod down the interior of the spring and around the exterior of the rod. The banner may be curved and posed by flexing the rod at the location of the spring. This curve is then retained in the banner by a balancing tension in the exterior portion of the elastic band between the ends of the rod. In some embodiments, the display arrangement is connected to one or more similar arrangements so that their banners form a continuous display.

Abstract: Methods of fabricating and prescribing lenses suitable for color blindness and dyslexia correction are disclosed. The corrective lens may be formed of an optically transparent base material, which is tinted to a desired color for correction by immersion in a colorant dye. The color tinted lens is then tinted by a neutral tint dye to render the lens observable as a regular corrective lens. Prescription of such lenses may be based on a dynamically balanced, or haploscopic, fashion of prescription that comprises selecting a first visual filter from a set of sixteen filters and a second visual filter from the remaining set of fifteen filters, the first for the dominant eye and the second for non-dominant eye.

Abstract: An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided.