Patents by Inventor Andrew Henry Wottreng
Andrew Henry Wottreng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8645667Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: GrantFiled: July 16, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
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Patent number: 8589657Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: GrantFiled: January 4, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
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Publication number: 20120284465Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
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Publication number: 20120173842Abstract: An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.Type: ApplicationFiled: January 4, 2011Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Bradly George Frey, Michal Ostrowski, Andrew Henry Wottreng
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Patent number: 8103835Abstract: Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.Type: GrantFiled: October 11, 2010Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Scott Douglas Clark, Andrew Henry Wottreng
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Patent number: 8028118Abstract: Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.Type: GrantFiled: December 5, 2007Date of Patent: September 27, 2011Assignee: Internation Business Machines CorporationInventors: Timothy Hume Heil, James Allen Rose, Andrew Henry Wottreng
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Publication number: 20110029738Abstract: Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.Type: ApplicationFiled: October 11, 2010Publication date: February 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Scott Douglas Clark, Andrew Henry Wottreng
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Patent number: 7827343Abstract: The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.Type: GrantFiled: September 20, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Bradly George Frey, Steven Mark Thurber, Andrew Henry Wottreng
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Patent number: 7814279Abstract: Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.Type: GrantFiled: March 23, 2006Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Scott Douglas Clark, Andrew Henry Wottreng
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Patent number: 7757006Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.Type: GrantFiled: November 21, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
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Patent number: 7552269Abstract: In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.Type: GrantFiled: January 11, 2007Date of Patent: June 23, 2009Assignee: International Business Machines CorporationInventors: Steven Mark Thurber, Andrew Henry Wottreng
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Publication number: 20090150642Abstract: Embodiments of the invention provide methods and apparatus for increasing the number of page attributes specified by a page table while minimizing an increase in size of the page table. According to embodiments of the invention, attribute index bits may be included within a page table and may be used to determine page attributes stored within an attribute index. Additionally, embodiments of the invention provide a plurality of new page attributes.Type: ApplicationFiled: December 5, 2007Publication date: June 11, 2009Inventors: Timothy Hume Heil, James Allen Rose, Andrew Henry Wottreng
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Publication number: 20090144452Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.Type: ApplicationFiled: November 21, 2008Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
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Patent number: 7530068Abstract: A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.Type: GrantFiled: December 17, 2003Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Scott Douglas Clark, Michael Norman Day, Charles Ray Johns, Andrew Henry Wottreng
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Publication number: 20090083471Abstract: The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.Type: ApplicationFiled: September 20, 2007Publication date: March 26, 2009Inventors: Bradly George Frey, Steven Mark Thurber, Andrew Henry Wottreng
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Patent number: 7475161Abstract: A method, apparatus and computer program product are provided for implementing conditional packet alterations based upon a transmit port. A selection mechanism is provided for implementing packet alterations. A sequence of frame alteration instructions and transmit port numbers associated with a packet being transmitted is applied to the selection mechanism. The selection mechanism performs alterations on the packet being transmitted responsive to the applied sequence of frame alteration instructions and port numbers associated with the packet. The selection mechanism includes a multiplexer that sequentially receives frame alteration instructions and port numbers associated with a packet being transmitted, and an indirect data array for providing packet alteration data from the indirect data array.Type: GrantFiled: September 4, 2003Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Kerry Christopher Imming, John David Irish, Tolga Ozguner, Andrew Henry Wottreng
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Publication number: 20080172507Abstract: In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Inventors: Steven Mark Thurber, Andrew Henry Wottreng
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Patent number: 6697935Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.Type: GrantFiled: October 23, 1997Date of Patent: February 24, 2004Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng
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Patent number: 6567839Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch can occur. Upon the occurrence of a thread switch event, the state and priority of all threads are dynamically interrogated to determine which thread should be the active thread executing the processor. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time.Type: GrantFiled: October 23, 1997Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Sheldon Bernard Levenstein, Andrew Henry Wottreng
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Patent number: 6212544Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive unproductive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.Type: GrantFiled: October 23, 1997Date of Patent: April 3, 2001Assignee: International Business Machines CorporationInventors: John Michael Borkenhagen, William Thomas Flynn, Andrew Henry Wottreng