Abstract: A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).

Abstract: A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).

Abstract: A method of writing a plurality of data values to a plurality of non-volatile memory modules connected to a processor includes initiating writing of a first data value to a first non-volatile memory array and delaying processing by the processor for a predetermined time to allow the first data value to be written to the first non-volatile memory array. The method further includes initiating writing of a second data value to a second non-volatile memory array before delaying processing by the processor to allow the processor to delay processing while both the first data value and the second data value are being written.