Patents by Inventor Andrew J. Bonthron

Andrew J. Bonthron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8703540
    Abstract: A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: April 22, 2014
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Patent number: 8593221
    Abstract: Examples of circuits and methods are provided for common mode stability and bandwidth broadening. A current generator circuit may include a first and a second transistor. Each of the first and second transistors includes a first, second, and third terminal. The first and second transistors provide a first and a second output current at their corresponding third terminals. A first branch including a first resistor and a first capacitor coupled in series is coupled between the third terminal of the first transistor and the first terminal of the second transistor. A second branch including a second resistor and a second capacitor coupled in series is coupled between the third terminal of the second transistor and the first terminal of the first transistor. The first and the second branches are configured to enable the current generator circuit to provide the first and second currents with improved common mode stability.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 26, 2013
    Assignee: Semtech Corporation
    Inventors: Liping Zhang, Thomas W. Krawczyk, Andrew J. Bonthron, David A. Rowe
  • Patent number: 8367469
    Abstract: A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: February 5, 2013
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Publication number: 20120115279
    Abstract: A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Application
    Filed: January 10, 2012
    Publication date: May 10, 2012
    Applicant: Semtech Corporation
    Inventors: Andrew J. BONTHRON, Darren Jay WALWORTH
  • Patent number: 8093714
    Abstract: A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: January 10, 2012
    Assignee: Semtech Corporation
    Inventors: Andrew J. Bonthron, Darren Jay Walworth
  • Publication number: 20110140260
    Abstract: A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: SIERRA MONOLITHICS, INC.
    Inventors: Andrew J. Bonthron, Darren Jay Walworth