Patents by Inventor Andrew J. Browne

Andrew J. Browne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250090278
    Abstract: The invention relates to dental bone grafting devices and magnesium meshes having features that are designed to corrode and/or absorb progressively, e.g., in stages, in order to improve dental bone regeneration, as well as methods for preparing the meshes. The meshes include a framework, and a geometric design is formed within the framework that includes design features. The geometric design and design features are selected and manipulated to provide the progressive corrosion and/or absorption profile of the mesh.
    Type: Application
    Filed: July 18, 2022
    Publication date: March 20, 2025
    Inventors: Andrew J. BROWN, Charles S. SFEIR, Kelly Bolden WILLIAMS
  • Publication number: 20250043303
    Abstract: The invention provides plants comprising transgenic event MON 88302 that exhibit tolerance to glyphosate herbicide. The invention also provides seeds, plant parts, cells, commodity products, and methods related to the event. The invention also provides DNA molecules that are unique to the event and were created by the insertion of transgenic DNA into the genome of a Brassica napus plant.
    Type: Application
    Filed: August 29, 2024
    Publication date: February 6, 2025
    Inventors: Andrew J. Brown, James F. Byrne, Robert H. Cole, James H. Crowley, John A. Miklos, Robert C. Ripley, Simone Seifert-Higgins, Jiali Xie
  • Patent number: 12110496
    Abstract: The invention provides plants comprising transgenic event MON 88302 that exhibit tolerance to glyphosate herbicide. The invention also provides seeds, plant parts, cells, commodity products, and methods related to the event. The invention also provides DNA molecules that are unique to the event and were created by the insertion of transgenic DNA into the genome of a Brassica napus plant.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 8, 2024
    Assignee: Monsanto Technology LLC
    Inventors: Andrew J. Brown, James F. Byrne, Robert H. Cole, James H. Crowley, John A. Miklos, Robert C. Ripley, Simone Seifert-Higgins, Jiali Xie
  • Patent number: 11881463
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 23, 2024
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Publication number: 20240014149
    Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Aleksandar ALEKSOV, Thomas SOUNART, Kristof DARMAWIKARTA, Henning BRAUNISCH, Prithwish CHATTERJEE, Andrew J. BROWN
  • Patent number: 11862552
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Patent number: 11824013
    Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: November 21, 2023
    Assignee: Intel Corporation
    Inventors: Lauren A. Link, Andrew J. Brown, Sheng C. Li, Sandeep B. Sane
  • Patent number: 11804455
    Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Thomas Sounart, Kristof Darmawikarta, Henning Braunisch, Prithwish Chatterjee, Andrew J. Brown
  • Patent number: 11705389
    Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Luke Garner, Liwei Cheng, Lauren Link, Cheng Xu, Ying Wang, Bin Zou, Chong Zhang
  • Patent number: 11670504
    Abstract: A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 ?m in thickness, and a second electrode is over the cured PID.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Brandon C. Marin, Andrew J. Brown, Dilan Seneviratne
  • Patent number: 11651902
    Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Andrew J. Brown, Prithwish Chatterjee, Sai Vadlamani, Lauren Link
  • Patent number: 11622448
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Tarek Ibrahim, Srinivas Pietambaram, Andrew J. Brown, Gang Duan, Jeremy Ecton, Sheng C. Li
  • Publication number: 20230094767
    Abstract: The invention relates to magnesium screws and screw-like devices for dental implant surgery and, more particularly, to magnesium and magnesium-based tenting devices for implementation in periosteal and gingival tissue overlying an alveolar ridge of a mandible or maxilla to provide vertical ridge augmentation, i.e., bone regeneration. The tenting devices may be composed of magnesium in dry form, such as metallic magnesium and salts thereof; or magnesium alloy including magnesium in dry form and at least one alloying element or compound; or magnesium-polymer composite including magnesium in dry form and at least one polymer.
    Type: Application
    Filed: March 16, 2021
    Publication date: March 30, 2023
    Applicant: UNIVERSITY OF PITTSBURGH - OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
    Inventors: Charles S. SFEIR, Andrew J. BROWN
  • Patent number: 11610706
    Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Kyu Oh Lee, Sheng C. Li, Andrew J. Brown, Lauren A. Link
  • Patent number: 11574874
    Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Robert A. May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong, Praneeth Akkinepally, Andrew J. Brown, Lauren A. Link, Prithwish Chatterjee
  • Patent number: 11552010
    Abstract: The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ?100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Robert A. May, Andrew J. Brown, Sri Ranga Sai Boyapati, Kristof Darmawikarta
  • Patent number: 11495552
    Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Thomas Sounart, Kristof Darmawikarta, Henning Braunisch, Prithwish Chatterjee, Andrew J. Brown
  • Publication number: 20220230951
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li
  • Publication number: 20220154205
    Abstract: The invention provides plants comprising transgenic event MON 88302 that exhibit tolerance to glyphosate herbicide. The invention also provides seeds, plant parts, cells, commodity products, and methods related to the event. The invention also provides DNA molecules that are unique to the event and were created by the insertion of transgenic DNA into the genome of a Brassica napus plant.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 19, 2022
    Inventors: Andrew J. BROWN, James F. BYRNE, Robert H. COLE, James H. CROWLEY, John A. MIKLOS, Robert C. RIPLEY, Simone SEIFERT-HIGGINS, Jiali XIE
  • Patent number: 11335632
    Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Prithwish Chatterjee, Junnan Zhao, Sai Vadlamani, Ying Wang, Rahul Jain, Andrew J. Brown, Lauren A. Link, Cheng Xu, Sheng C. Li