Patents by Inventor Andrew J. Burstein

Andrew J. Burstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11381160
    Abstract: A method for controlling a switched tank converter (STC) includes (a) driving a first resonant tank circuit of the STC at a first frequency and with a first fixed on-time, to obtain a first fixed ratio of output voltage of the STC to input voltage of the STC, while the STC is powering a load having a first magnitude and (b) driving the first resonant tank circuit of the STC at a second frequency and with the first fixed on-time, to obtain the first fixed ratio of output voltage of the STC to input voltage of the STC while the STC is powering a load having a second magnitude. The second frequency is smaller than the first frequency, and the second magnitude is smaller than the first magnitude.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: July 5, 2022
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Salvatore G. Pastorina, Tonio Gaetano Biondi, Thurein Soe Paing, Andrea Pizzutelli, Michael D. McJimsey, Andrew J. Burstein
  • Publication number: 20200220461
    Abstract: A method for controlling a switched tank converter (STC) includes (a) driving a first resonant tank circuit of the STC at a first frequency and with a first fixed on-time, to obtain a first fixed ratio of output voltage of the STC to input voltage of the STC, while the STC is powering a load having a first magnitude and (b) driving the first resonant tank circuit of the STC at a second frequency and with the first fixed on-time, to obtain the first fixed ratio of output voltage of the STC to input voltage of the STC while the STC is powering a load having a second magnitude. The second frequency is smaller than the first frequency, and the second magnitude is smaller than the first magnitude.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 9, 2020
    Inventors: Salvatore G. Pastorina, Tonio Gaetano Biondi, Thurein Soe Paing, Andrea Pizzutelli, Michael D. McJimsey, Andrew J. Burstein
  • Patent number: 9559679
    Abstract: An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: January 31, 2017
    Assignee: Volterra Semiconductor, LLC
    Inventors: Alexandr Ikriannikov, Andrew J. Burstein, Anthony J. Stratakos
  • Publication number: 20150318248
    Abstract: An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 5, 2015
    Inventors: Alexandr Ikriannikov, Andrew J. Burstein, Anthony J. Stratakos
  • Patent number: 9083332
    Abstract: An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is included in an integrated electronic assembly.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 14, 2015
    Assignee: Volterra Semiconductor Corporation
    Inventors: Alexandr Ikriannikov, Andrew J. Burstein, Anthony J. Stratakos
  • Patent number: 9018912
    Abstract: The present system and method manage a rechargeable battery comprising two or more battery cells or series stacks of cells. The system includes a set of switches, each of which connects a cell or stack of cells between positive and negative nodes when actuated, or connects one cell in a stack of cells to another cell in the stack when actuated, such that when all the switches in a given stack are actuated, it is connected between the positive and negative nodes. An electrical load is directly connected to the positive and negative nodes. A controller determines the state of each cell or stack of cells by measuring and/or calculating one or more predetermined characteristics, and selectively actuates the switches based on the states of the cells or stacks of cells so as to enhance the life of the battery.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Inphi Corporation
    Inventors: Andrew J. Burstein, Lawrence Tse
  • Patent number: 8891022
    Abstract: Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: November 18, 2014
    Assignee: Telegent Systems, Inc.
    Inventors: Shaori Guo, Zu Bing Yuan, Andrew J. Burstein
  • Publication number: 20140152350
    Abstract: An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Alexandr Ikriannikov, Andrew J. Burstein, Anthony J. Stratakos
  • Publication number: 20120293130
    Abstract: The present system and method manage a rechargeable battery comprising two or more battery cells or series stacks of cells. The system includes a set of switches, each of which connects a cell or stack of cells between positive and negative nodes when actuated, or connects one cell in a stack of cells to another cell in the stack when actuated, such that when all the switches in a given stack are actuated, it is connected between the positive and negative nodes. An electrical load is directly connected to the positive and negative nodes. A controller determines the state of each cell or stack of cells by measuring and/or calculating one or more predetermined characteristics, and selectively actuates the switches based on the states of the cells or stacks of cells so as to enhance the life of the battery.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 22, 2012
    Inventors: ANDREW J. BURSTEIN, Lawrence Tse
  • Publication number: 20120033139
    Abstract: Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Inventors: Shaori GUO, Zu Bing Yuan, Andrew J. Burstein
  • Patent number: 7465621
    Abstract: A first impurity region of a first type is implanted to have a first surface area on a substrate. A second impurity region of an opposite second type is implanted into a drain region of the transistor to have a second surface area in the first surface area of the first impurity region. A gate oxide is formed after implantation of the second impurity region between a source region and the drain region of the transistor, and the gate oxide is covered with a conductive material. A third impurity region of the opposite second type and a fourth impurity region of the first type are implanted into the source region of the transistor in the first surface area. A fifth impurity region of the opposite second type is implanted into the drain region of the transistor in the second surface area of the second impurity region.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: December 16, 2008
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga, Andrew J. Burstein
  • Patent number: 7091736
    Abstract: A method and apparatus for determining a setting specified from a plurality of the settings for a function provided in an integrated circuit, wherein the setting is specified by connecting an external measurement resistor to a measurement terminal of the integrated circuit, comprises applying a direct current to the measurement terminal of the integrated circuit, thereby producing a measurement voltage at the measurement terminal; applying the direct current to a reference terminal of the integrated circuit, wherein the reference terminal has an external reference resistor connected thereto, thereby producing a reference voltage at the reference terminal; quantizing a voltage level of a difference voltage representing a voltage difference between the reference voltage and the measurement voltage, thereby producing a quantized voltage; and providing control signals to a functional module within the integrated circuit, the control signals representing the one of the settings corresponding to the quantized volta
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: August 15, 2006
    Assignee: Volterra Semiconductor Corporation
    Inventors: Jeremy M. Flasck, Andrew J. Burstein, David B. Lidsky, Michael D. McJimsey
  • Patent number: 7038274
    Abstract: A voltage regulator having an input terminal and an output terminal. A PMOS transistor connects the input terminal to an intermediate terminal. The PMOS transistor includes a first gate oxide layer. An LDMOS transistor connects the intermediate terminal to ground. The LDMOS transistor includes a second gate oxide layer. A controller drives the PMOS transistor and the LDMOS transistor to alternately couple the intermediate terminal between the input terminal and ground, to generate an intermediate voltage at the intermediate terminal having a rectangular waveform. A filter is disposed between the intermediate terminal and the output terminal to convert the rectangular waveform into a substantially DC voltage at the output terminal.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: May 2, 2006
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga, Andrew J. Burstein
  • Patent number: 6894501
    Abstract: A method and apparatus for determining a setting specified from a plurality of the settings for a function provided in an integrated circuit, wherein the setting is specified by connecting an external measurement resistor to a measurement terminal of the integrated circuit, comprises applying a direct current to the measurement terminal of the integrated circuit, thereby producing a measurement voltage at the measurement terminal; applying the direct current to a reference terminal of the integrated circuit, wherein the reference terminal has an external reference resistor connected thereto, thereby producing a reference voltage at the reference terminal; quantizing a voltage level of a difference voltage representing a voltage difference between the reference voltage and the measurement voltage, thereby producing a quantized voltage; and providing control signals to a functional module within the integrated circuit, the control signals representing the one of the settings corresponding to the quantized volta
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: May 17, 2005
    Assignee: Volterra Semiconductor, Inc.
    Inventors: Jeremy M. Flasck, Andrew J. Burstein, David B. Lidsky, Michael D. McJimsey
  • Patent number: 6853169
    Abstract: A digitally implemented voltage regulator having including a plurality of slaves coupled in parallel. Each slave includes a switching circuit that intermittently couples an input terminal and an output terminal of the voltage regulator in response to a digital control signal for the corresponding slave. A current sensor in each slave generates a digital first feedback signal derived from the current passing through the corresponding switching circuit. A digital controller receives and uses the digital feedback signals from the plurality of slaves to generate a digital control signal for each slave. The digital controller operates active slaves of the plurality of slaves at determined phase offsets to minimize voltage ripple and maintain the output voltage at the output terminal at a substantially constant level.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: February 8, 2005
    Assignee: Volterra Semiconductor Corporation
    Inventors: Andrew J. Burstein, David B. Lidsky, Anthony Stratakos, Charlie Sullivan, William Clark
  • Publication number: 20040052098
    Abstract: A digitally implemented voltage regulator in which a switching circuit intermittently couples the input terminal and the output terminal in response to a digital control signal. A current sensor generates a digital first feedback signal derived from the current passing through the switching circuit, and a voltage sensor generates a digital second feedback signal derived from the output voltage. A digital controller receives and uses the digital feedback signals to generate the digital control signal.
    Type: Application
    Filed: July 8, 2003
    Publication date: March 18, 2004
    Applicant: Volterra Semiconductors Corporation, a Delaware corporation
    Inventors: Andrew J. Burstein, David B. Lidsky, Anthony Stratakos, Charlie Sullivan, William Clark
  • Patent number: 6590369
    Abstract: A digitally implemented voltage regulator in which a switching circuit intermittently couples the input terminal and the output terminal in response to a digital control signal. A current sensor generates a digital first feedback signal derived from the current passing through the switching circuit, and a voltage sensor generates a digital second feedback signal derived from the output voltage. A digital controller receives and uses the digital feedback signals to generate the digital control signal.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: July 8, 2003
    Assignee: Volterra Semiconductor Corporation
    Inventors: Andrew J. Burstein, David B. Lidsky, Anthony Stratakos, Charlie Sullivan, William Clark
  • Patent number: 6525516
    Abstract: A voltage regulator has an input terminal, an output terminal, a first transistor to intermittently form an electrical circuit between the input terminal and the output terminal, a rectifier connecting an intermediate terminal in the electrical circuit between the input terminal and the output terminal to ground, a controller that drives the first transistor, and a capacitorless filter. Capacitance for the filter function can be provided by a capacitor, e.g., the input capacitor of the load, located in the load chip or on the same printed circuit board as the load chip. The capacitorless filter can include an inductor connected between the intermediate terminal and the output terminal, or the inductance can be provided by parasitic effects in the connections between the voltage regulator and load.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: February 25, 2003
    Assignee: Volterra Semiconductor Corporation
    Inventors: Aaron M. Schultz, Andrew J. Burstein, David B. Lidsky, Anthony J. Stratakos
  • Patent number: 6462522
    Abstract: A voltage regulator with an input terminal and an output terminal has a printed circuit board, a substrate mounted on the printed circuit board, and a first flip-chip type integrated circuit chip mounted on the substrate. The first integrated circuit chip includes a first power switch fabricated therein to alternately couple and decouple the input terminal to the output terminal. A filter is disposed to provide a substantially DC voltage at the output terminal, and a control circuit controls the power switch to maintain the DC voltage substantially constant.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: October 8, 2002
    Assignee: Volterra Semiconductor Corporation
    Inventors: Andrew J. Burstein, Charles Nickel
  • Patent number: 6445244
    Abstract: A sensor for measuring a current passing through a load. The sensor has a power transistor having a first terminal connected to substantially constant voltage and a second terminal connected to the load. The sensor can sample a voltage difference with a variable capacitor, and a controller can be configured to cause a variable capacitor in the current sensor to have a capacitance inversely proportional to a resistance of the power transistor, whereby a charge stored on the variable capacitor is proportional to the current passing through the power transistor when the sampling switches are opened. A comparator can compare the current through the power transistor to a known reference current to generate a digital output signal. The sensor can include a power transistor, reference transistor and amplifier connected and configured so as to generate a signal on a reference line having a current of known proportion to the current passing through the load.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: September 3, 2002
    Assignee: Volterra Semiconductor Corporation
    Inventors: Anthony Stratakos, Andrew J. Burstein, David B. Lidsky, Phong Nguyen, William Clark